High-performance CMOS current comparator

A new high-performance CMOS current comparator is proposed. By adding two inverters in the feedback loop of Traff's comparator, the proposed comparator exhibits significant speed improvement especially for low input currents. Simulated in a 0.18 mum CMOS technology, the comparator achieves a 0.6 ns delay for a 100 nA input current at 1.8 V supply, which is about eight times faster than Traff's comparator.     

一种高精度动态CMOS比较器的设计与研制

比较器的设计对于A／D、D／A转换器的精度至关重要。为满足14位高分辨率A／D转换器的需要，设计了一种高精度动态CMOS比较器，采用二级差分比较和一级动态正反馈latch结构实现了高比较精度。预增益和Latch级的应用降低了功耗。设计中充分考虑了工艺离散性和使用环境温度与电源变化的影响，保证了成品率和电路在变化工作环境下性能指标的实现。仿真结果表明，设计的高速动态比较器LSB（Least Significant Bit）为±0．15mV，输入动态范围为VSS-VDD（VSS为地电压，VDD为电源电压），相应于14位比较精度。功耗6．28mW，工作频率3．6MHz。电路用0．6μm双层金属、双层多晶硅CMOS工艺实现。     

A precision variable-supply CMOS comparator

Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.     

High performance CMOS current comparator

A new high-speed CMOS current comparator is described. By changing the buffer of an existing comparator from class B to class AB operation, voltage swings are reduced, resulting in greater speed for small input currents. Simulation results employing a 1.6μm CMOS technology show the response time to a 0.1μA input current to be 11ns and the power dissipation to be 1.4mW, resulting in a five times improvement in speed/power ratio over existing high-speed current comparators     

Accurate low-power CMOS autozeroed comparator

A low-power CMOS autozeroed comparator suitable for high-frequency A/D convertors is discussed. The use of a source follower in the autozeroed inverter stage allows the circuit to provide an optimum tradeoff between speed, gain and power dissipation. Relationships are given that relate the time response, both in the autozeroing and comparating phase, to the circuit parameters. An experimental prototype, fabricated with a 2 mu m CMOS process is also presented.<>     

Simple high-speed CMOS current comparator

A simple modification to an existing current comparator is proposed, which enables a very low response time to be achieved with a minimal increase in circuit complexity. Circuit simulations allowed the design approach to be validated and the comparator performance to be compared to those of two other existing comparators     

0.6μm CMOS工艺迟滞比较器的失配分析

本文对一个采用0.6μm CMOS工艺的迟滞比较器的失配性能进行了理论分析,探讨了关键部件的尺寸失配对该比较器迟滞性能的影响.Hspice仿真证明了理论分析的正确性;Monte Carlo仿真进一步分析了该比较器性能对失配参数的敏感性.本文的工作为今后的抗失配设计改进提供了方向.     

High-performance single clock cycle CMOS comparator

A novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm. Fast dynamic NOR gates are used instead of high-fanin NAND gates and this results in significant improvement in performance over the traditional design. The design was realised in AMS 0.35 /spl mu/m technology. It is shown that the proposed design is 22% faster than the existing fastest single-cycle comparator based on priority encoder.     

A 100-MHz pipelined CMOS comparator

The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2-μm CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate     

Design considerations for a high-speed CMOS comparator

Design considerations for a high-speed CMOS comparator for application in highspeed analogue-to-digital conversion are presented. Extensive simulations show that the comparator designed accordingly operates well above 250MHz clock speed in standard 0.5µm CMOS technology. An accuracy of 5mV and average power consumption of 0.3mW on 3.3V power supply is observed using simulations when it operates at 250MHz.     

High performance CMOS current comparator using resistive feedbacknetwork

A new high speed, low power and small area CMOS current comparator based on a resistive feedback network is proposed. Simulation results employing 0.35 μm CMOS parameters demonstrate 7 ns response time and 0.45 mW power consumption for 0.1 μA input current, which represents a ~400% improvement in power-delay product over existing current comparators. In this design, the bias current and the input impedance are well controlled parameters, and the inherent autozeroing scheme does not require any offset compensation     

A high-speed CMOS comparator with 8-b resolution

A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5-μm n-well process with a die area of only 140×100 μm². This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore ±0.5 LSB resolution is equal to ±4.9 mV)     

一种CMOS动态闩锁电压比较器的优化设计

提出了一种应用于Pipeline ADC和Sigma-Delta ADC中改进的动态闩锁电压比较器。采用0.35μm CMOS N阱工艺设计,工作于2.5V单电源电压。通过详细的分析和优化,使比较器具有较小的输入失调电压和踢回噪声,仿真结果表明它的输入失调电压分布范围为28.6mV,最高工作频率200MHz、功耗230μW。     

A high-speed CMOS comparator for use in an ADC

A dynamic latch preceded by an offset-cancelled amplifier is used in the 3-μm CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

一种带三级预放大的高速高精度CMOS比较器

比较器的设计对于A/D,D/A转换器的精度至关重要。为了满足12位高分辨率的A/D转换器的需要,设计了一种高精度CMOS比较器,采用三级差分比较和一级动态正反馈的Latch结构实现了高比较精度。论文对该比较器的电路结构,增益,带宽,输入失调消除原理和锁存时间常数进行了分析,并利用Hynix 0.5um CMOS工艺提供的器件模型进行了仿真,在20MHZ频率下,比较器的精度达到了400uV。测试结果显示,在16MHZ频率下,比较器的精度达到了600uV。在电源电压为5V时,功耗为78uw。芯片面积是210um *180um 。该比较器已经成功用于一种10MSPS 12位A/D转换器中。该器件还可以用于13位以下的其他A/D转换器电路。     

一种高速低功耗迟滞CMOS比较器的分析与设计

文章分析设计了一种具有内部迟滞效应的高速低功耗CMOS比较器,该比较器采用前置放大级、正反馈级和输出驱动级级联的结构,实现了对增益、速度和功耗的优化.电路的内部迟滞效应有效的实现了对噪声信号的抑制.采用0.35μm CMOS工艺的仿真结果表明,该比较器在3.3V的供电电源下可达到100MHz的工作速度.在20MHz的采样速率下具有0.2mW的功耗.芯片测试结果表明各项性能指标均达到了设计要求.     

一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器

提出了一种应用于CMOS D类音频功率放大器的Rail-to-Rail PWM比较器,其输入级为Rail-to-Rail结构,输出级为AB类输出。基于CSMC 0.5μm CMOS工艺的BSIM3V3 Spice模型,采用Hspice对PWM比较器的特性进行了仿真,典型模型下的直流开环增益为50dB,电源抑制比为52dB,ICMR为0.04V~4.98V,传输时延为24.5ns,版图有效面积为210×75μm2。由于PWM比较器的良好性能参数,所以其不仅适用于D类音频功率放大器,也能应用于各类低频数据转换电路。     

Performance analysis of a color CMOS photogate image sensor

The performance of a color CMOS photogate image sensor is reported. It is shown that by using two levels of correlated-double sampling it is possible to effectively cancel all fixed-pattern noise due to read-out circuit mismatch. Instead the fixed-pattern noise performance of the sensor is limited by dark current nonuniformity at low signal levels, and conversion gain nonuniformity at high signal levels. It is further shown that the imaging performance of the sensor is comparable to low-end CCD sensors but inferior to that reported for high-end CCD sensors due to low quantum efficiency, high dark current, and pixel cross-talk. As such the performance of CMOS sensors is limited at the device level rather than at the architectural level. If the imaging performance issues can be addressed at the fabrication process level without increasing cost or degrading transistor performance, CMOS has the potential to seriously challenge CCD as the solid-state imaging technology of choice due to low power dissipation and compatibility with camera system integration     

Vibrational analysis of angle measurement comparator

The comparators of angle measurement are designed for measurement of angle gauges (limbs) and angular movements (turning) for calibration measurement errors of measuring systems. The vibration isolation issue for angle comparators is particularly relevant. Vibration analysis became essential for angle comparators operating in dynamic mode and used for precise angular measurements. In this paper, an analysis of wavelet intensity distributions of angle comparators is carried out by applying the theory of covariance functions. Data from measurements of vibrational signals at fixed points were acquired in the form of data arrays (matrices). Estimates of covariance functions between the arrays of data and the estimates of covariance functions of single arrays were calculated upon changing the quantization interval on the time scale. For signal processing, MATLAB 7 software was applied.