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1.
This paper proposes an accurate tunable‐gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10‐bit digital code. The 1/x circuit was fabricated using a 0.18 μm CMOS process. Its core area is , and it consumes 278 μW at and . Its error is within 1.7% at to 1 V.  相似文献   

2.
This letter proposes a novel calibration method for a multiport amplifier (MPA) to achieve optimum port‐to‐port isolation by correcting both the amplitude and phase of the calibration signals. The proposed architecture allows for the detection of the phase error and amplitude error in each RF signal path simultaneously and can enhance the calibrated resolution by controlling the analog phase shifters and attenuators. The designed and MPAs show isolation characteristics of 30 dB and 27 dB over a frequency range of 19.5 GHz to 22.5 GHz, respectively.  相似文献   

3.
This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.  相似文献   

4.
This paper presents a 5‐bit digital step attenuator (DSA) using a commercial 0.18‐μm silicon‐on‐insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T‐type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is , including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC‐to‐20‐GHz SOI DSA.  相似文献   

5.
This paper presents a low‐complexity channel‐adaptive reconfigurable QR‐decomposition and M‐algorithm‐based maximum likelihood detection (QRM‐MLD) multiple‐input and multiple‐output (MIMO) detector. Two novel design approaches for low‐power QRM‐MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM‐MLD MIMO detector (where the M‐value represents the number of survival branches in a stage) for dynamically adapting to time‐varying channels is also proposed in this work. The proposed reconfigurable QRM‐MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM‐based QRM‐MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of MIMO with 64‐QAM. Under time‐varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.  相似文献   

6.
This paper presents a compact structure composed of an upper high‐impedance transmission line, a middle extended parallel coupled line, and a pair of inter‐coupled symmetrical stepped impedance stubs. Detailed investigation into this structure based on an equivalent circuit analysis reveals that this proposed structure exhibits a quasi‐elliptic low‐pass filtering response with three transmission zeros. Moreover, the positions of the three transmission zeros can be tuned and reallocated flexibly by choosing the proper circuit parameters. Finally, the design concept is validated through the design, fabrication, and measurement of two exemplary low‐pass filters (LPFs) with one single unit and two cascaded asymmetric units. The measured results agree well with the simulated results. In addition, in the range of 1.42 fc to 7.03 fc, the fabricated quasi‐elliptic LPFs experimentally demonstrate a very wide upper‐stopband of 20 dB using a compact size of only , where λg is the guided wavelength of a 50 Ω transmission line at the central frequency.  相似文献   

7.
A miniaturized triple‐band antenna suitable for wireless USB dongle applications is proposed and investigated in this paper. The presented antenna, simply consisting of a circular‐arc‐shaped stub, an L‐shaped stub, a microstrip feed line, and a rectangular ground plane has a compact size of and is capable of generating three separate resonant modes with very good impedance matching. The measurement results show that the antenna has several impedance bandwidths for of 260 MHz (2.24 GHz to 2.5 GHz), 320 MHz (3.4 GHz to 3.72 GHz), and 990 MHz (5.1 GHz to 6.09 GHz), which can be applied to both 2.4/5.2/5.8 GHz WLAN bands and 3.5/5.5 GHz WiMAX bands. Moreover, nearly‐omni‐directional radiation patterns and stable gain across the operating bands can be obtained.  相似文献   

8.
We present a cost‐effective dual polarization quadrature phase‐shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two 90° optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of 2%‐Δ. Two four‐channel spot‐size converter integrated waveguide‐photodetector (PD) arrays are bonded on PD carriers for transverse‐electric/transverse‐magnetic polarization, and butt‐coupled to a polished facet of the PLC using a simple chip‐to‐chip bonding method. Instead of a ceramic sub‐mount, a low‐cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans‐impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3‐dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of is achieved at a 112‐Gbps back‐to‐back transmission with off‐line digital signal processing.  相似文献   

9.
In this paper, we propose a convenient microwave orbital angular momentum (OAM) mode generation and multiplexing method operating in the 18 GHz frequency band, based on a uniform circular array and a Butler matrix. The three OAM modes ?1, 0, and +1 were generated and verified using spatial S‐parameter measurements; the measured back‐to‐back mode isolation was greater than 17 dB in the full 17 GHz to 19 GHz range. However, the radiated OAM beam centers were slightly dislocated and varied with both frequency and the mode index, because of the non‐ideal characteristics of the Butler matrix. This resulted in mode isolation degradation and transmission distance limitations.  相似文献   

10.
Using a sub‐terahertz (sub‐THz) wave generated using a photonics‐based technology, a high‐speed wireless link operating at up to 10 Gbps is designed and demonstrated for realization of seamless connectivity between wireless and wired networks. The sub‐THz region is focused upon because of the possibility to obtain sufficient bandwidth without interference with the allocated RF bands. To verify the high‐speed wireless link, such dynamic characteristics as the eye diagrams and bit error rate (BER) are measured at up to 10 Gbps for non‐return‐to‐zero pseudorandom binary sequence data. From the measurement results, a receiver sensitivity of –23.5 dBm at is observed without any error corrections when the link distance between the transmitter and receiver is 3 m. Consequently, we hope that our design and experiment results will be helpful in implementing a high‐speed wireless link using a sub‐THz wave.  相似文献   

11.
Blind mismatch correction of time‐interleaved analog‐to‐digital converters (TI‐ADC) is a challenging task. We present a practical blind calibration technique for low‐computation, low‐complexity, and high‐resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI‐ADC channels and most real‐life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed‐domain error correction. The proposed technique is experimentally verified by an 400 MSPS TI‐ADC system. In a single‐tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.  相似文献   

12.
In this work, we develop a simulation method to predict a two‐dimensional luminance distribution method using a circuitry simulation. Based on the simulation results, we successfully fabricate large area transparent organic light‐emitting diode panels with high luminance uniformity.  相似文献   

13.
A novel microstrip low‐pass filter is presented to achieve an ultra‐wide stopband with 11 harmonic suppression and very sharp skirt characteristics. The filter is composed of a modified U‐shaped resonator (which creates two fully adjustable transmission zeroes), a T‐shaped resonator (which determines a cut‐off frequency), and four radial stubs (which provide a wider stopband). The operating mechanism of the filter is investigated based on a proposed equivalent‐circuit model, and the role of each section of the proposed filter in creating null points is theoretically discussed in detail. The presented filter with 3 dB cut‐off frequency has been fabricated and measured. Results show that a relative stopband bandwidth of 164% (referred to as a 22 dB suppression) is obtained while achieving a high figure‐of‐merit of 15,221.  相似文献   

14.
This letter describes a two‐phase clock oxide thin‐film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART‐SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from ?4 V to 5 V at a line time of 5 μs. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively ?12.6 dB and ?26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16‐stage shift registers at , compared to 11.5 mW for the conventional circuits.  相似文献   

15.
This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) technology. The RFID logic circuit generates 16‐bit code programmed in read‐only memory. All circuits are implemented in a pseudo‐CMOS logic style using transparent a‐IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300‐nm to 800‐nm wavelength. The RFID logic chip generates Manchester‐encoded 16‐bit data with a 3.2‐kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm2.  相似文献   

16.
This paper presents a new locomotion mode recognition method based on a transformed correlation feature analysis using an electromyography (EMG) pattern. Each movement is recognized using six weighted subcorrelation filters, which are applied to the correlation feature analysis through the use of six time‐domain features. The proposed method has a high recognition rate because it reflects the importance of the different features according to the movements and thereby enables one to recognize real‐time EMG patterns, owing to the rapid execution of the correlation feature analysis. The experiment results show that the discriminating power of the proposed method is 85.89% when walking on a level surface, 96.47% when going up stairs, and 96.37% when going down stairs for given normal movement data. This makes its accuracy and stability better than that found for the principal component analysis and linear discriminant analysis methods.  相似文献   

17.
In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).  相似文献   

18.
A Ka‐band 6‐W high power microwave monolithic integrated circuit amplifier for use in a very small aperture terminal system requiring high linearity is designed and fabricated using commercial 0.15‐μm GaAs pHEMT technology. This three‐stage amplifier, with a chip size of 22.1 mm2 can achieve a saturated output power of 6 W with a 21% power‐added efficiency and 15‐dB small signal gain over a frequency range of 28.5 GHz to 30.5 GHz. To obtain high linearity, the amplifier employs a class‐A bias and demonstrates an output third‐order intercept point of greater than 43.5 dBm over the above‐mentioned frequency range.  相似文献   

19.
In this letter, we present low‐temperature grown GaAs (LTG‐GaAs)‐based photoconductive antennas for the generation and detection of terahertz (THz) waves. The growth of LTG‐GaAs and the annealing temperatures are systematically discussed based on the material characteristics and the properties of THz emission and detection. The optimum annealing temperature depends on the growth temperature, which turns out to be 540°C to 580°C for the initial excess arsenic density of to .  相似文献   

20.
We present the design and fabrication of a 60 GHz medium power amplifier monolithic microwave integrated circuit with excellent gain‐flatness for a 60 GHz radio‐over‐fiber system. The circuit has a 4‐stage structure using microstrip coupled lines instead of metal‐insulator‐metal capacitors for unconditional stability of the amplifier and yield enhancement. The gains of each stage of the amplifier are modified to provide broadband characteristics of input/output matching for the first and fourth stages and to achieve higher gains for the second and third stages to improve the gain‐flatness of the amplifier for wideband.  相似文献   

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