AlGaN/GaN Based Ultra‐wideband 15‐W High‐Power Amplifier with Improved Return Loss

An ultra‐wideband microwave monolithic integrated circuit high‐power amplifier with excellent input and output return losses for phased array jammer applications was designed and fabricated using commercial 0.25‐μm AlGaN/GaN technology. To improve the wideband performance, resistive matching and a shunt feedback circuit are employed. The input and output return losses were improved through a balanced design using Lange‐couplers. This three‐stage amplifier can achieve an average saturated output power of 15 W, and power added efficiency of 10% to 28%, in a continuous wave operation over a frequency range of 6 GHz to 18 GHz. The input and output return losses were demonstrated to be lower than over a wide frequency range.     

Adaptive Calibration Method in Multiport Amplifier for K‐Band Payload Applications

This letter proposes a novel calibration method for a multiport amplifier (MPA) to achieve optimum port‐to‐port isolation by correcting both the amplitude and phase of the calibration signals. The proposed architecture allows for the detection of the phase error and amplitude error in each RF signal path simultaneously and can enhance the calibrated resolution by controlling the analog phase shifters and attenuators. The designed and MPAs show isolation characteristics of 30 dB and 27 dB over a frequency range of 19.5 GHz to 22.5 GHz, respectively.     

Microwave Orbital Angular Momentum Mode Generation and Multiplexing Using a Waveguide Butler Matrix

In this paper, we propose a convenient microwave orbital angular momentum (OAM) mode generation and multiplexing method operating in the 18 GHz frequency band, based on a uniform circular array and a Butler matrix. The three OAM modes ?1, 0, and +1 were generated and verified using spatial S‐parameter measurements; the measured back‐to‐back mode isolation was greater than 17 dB in the full 17 GHz to 19 GHz range. However, the radiated OAM beam centers were slightly dislocated and varied with both frequency and the mode index, because of the non‐ideal characteristics of the Butler matrix. This resulted in mode isolation degradation and transmission distance limitations.     

A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18‐μm SOI CMOS Technology

This paper presents a 5‐bit digital step attenuator (DSA) using a commercial 0.18‐μm silicon‐on‐insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T‐type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is , including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC‐to‐20‐GHz SOI DSA.     

A Transparent Logic Circuit for RFID Tag in a‐IGZO TFT Technology

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) technology. The RFID logic circuit generates 16‐bit code programmed in read‐only memory. All circuits are implemented in a pseudo‐CMOS logic style using transparent a‐IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300‐nm to 800‐nm wavelength. The RFID logic chip generates Manchester‐encoded 16‐bit data with a 3.2‐kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm².     

Compact Triple‐Band Monopole Antenna for WLAN/WiMAX‐Band USB Dongle Applications

A miniaturized triple‐band antenna suitable for wireless USB dongle applications is proposed and investigated in this paper. The presented antenna, simply consisting of a circular‐arc‐shaped stub, an L‐shaped stub, a microstrip feed line, and a rectangular ground plane has a compact size of and is capable of generating three separate resonant modes with very good impedance matching. The measurement results show that the antenna has several impedance bandwidths for of 260 MHz (2.24 GHz to 2.5 GHz), 320 MHz (3.4 GHz to 3.72 GHz), and 990 MHz (5.1 GHz to 6.09 GHz), which can be applied to both 2.4/5.2/5.8 GHz WLAN bands and 3.5/5.5 GHz WiMAX bands. Moreover, nearly‐omni‐directional radiation patterns and stable gain across the operating bands can be obtained.     

Analysis of Novel Approach to Design of Ultra‐wide Stopband Microstrip Low‐Pass Filter Using Modified U‐Shaped Resonator

A novel microstrip low‐pass filter is presented to achieve an ultra‐wide stopband with 11 harmonic suppression and very sharp skirt characteristics. The filter is composed of a modified U‐shaped resonator (which creates two fully adjustable transmission zeroes), a T‐shaped resonator (which determines a cut‐off frequency), and four radial stubs (which provide a wider stopband). The operating mechanism of the filter is investigated based on a proposed equivalent‐circuit model, and the role of each section of the proposed filter in creating null points is theoretically discussed in detail. The presented filter with 3 dB cut‐off frequency has been fabricated and measured. Results show that a relative stopband bandwidth of 164% (referred to as a 22 dB suppression) is obtained while achieving a high figure‐of‐merit of 15,221.     

Pseudo Optical PAM‐N Signal Using Externally Modulated Lasers

We propose a pseudo optical N‐level pulse‐amplitude modulation (PO PAM‐N) signal using a few externally‐modulated lasers (EMLs) operating at different wavelengths, which is suitable for upgrading the transmission speed over an optical link of ＜ 10 km single‐mode fiber with low‐cost components. To compare a PO PAM‐N signal with that of a standard optical PAM‐N signal, we perform experiments for evaluating the performance of a 51.56‐Gb/s PO PAM‐4 signal and standard 51.56‐Gb/s optical PAM‐4 signal. The receiver sensitivity (at ) of the PO PAM‐4 signal is 1.5 dB better than the receiver sensitivity of a standard optical PAM‐4 signal. We also investigate the feasibility of PO PAM‐N signals operating at 103.12 Gb/s, considering relative intensity noise, timing jitter, extinction ratio (ER) of EMLs, and dispersion. From the results, a PO PAM‐8 signal performs better than PO PAM‐4 and PO PAM‐16 signals at 103.12 Gb/s. Finally, we suggest a timing control method to suppress the effect of dispersion in a PO PAM‐N signal. We show that the tolerance to dispersion of a 103.12‐Gb/s PO PAM‐8 signal can be improved to ±40 ps/nm by applying a proposed scheme.     

Robust Two‐Phase Clock Oxide TFT Shift Register over Threshold Voltage Variation and Clock Coupling Noises

This letter describes a two‐phase clock oxide thin‐film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART‐SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from ?4 V to 5 V at a line time of 5 μs. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively ?12.6 dB and ?26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16‐stage shift registers at , compared to 11.5 mW for the conventional circuits.     

Design and Experiment Results of High‐Speed Wireless Link Using Sub‐terahertz Wave Generated by Photonics‐Based Technology

Using a sub‐terahertz (sub‐THz) wave generated using a photonics‐based technology, a high‐speed wireless link operating at up to 10 Gbps is designed and demonstrated for realization of seamless connectivity between wireless and wired networks. The sub‐THz region is focused upon because of the possibility to obtain sufficient bandwidth without interference with the allocated RF bands. To verify the high‐speed wireless link, such dynamic characteristics as the eye diagrams and bit error rate (BER) are measured at up to 10 Gbps for non‐return‐to‐zero pseudorandom binary sequence data. From the measurement results, a receiver sensitivity of –23.5 dBm at is observed without any error corrections when the link distance between the transmitter and receiver is 3 m. Consequently, we hope that our design and experiment results will be helpful in implementing a high‐speed wireless link using a sub‐THz wave.     

Accurate Tunable‐Gain 1/x Circuit Using Capacitor Charging Scheme

This paper proposes an accurate tunable‐gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10‐bit digital code. The 1/x circuit was fabricated using a 0.18 μm CMOS process. Its core area is , and it consumes 278 μW at and . Its error is within 1.7% at to 1 V.     

Design Space Exploration for NoC‐Style Bus Networks

With the number of IP cores in a multicore system‐on‐chip increasing to up to tens or hundreds, the role of on‐chip interconnection networks is vital. We propose a networks‐on‐chip‐style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade‐off for the time saving, the time cost (TC) of the searched architecture is increased to up to and , respectively, at each step compared with that of the architecture obtained through full‐case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to when compared with that obtained through full‐case exploration.     

Highly Simplified and Bandwidth‐Efficient Human Body Communications Based on IEEE 802.15.6 WBAN Standard

This paper presents a transmission method for improving human body communications in terms of spectral efficiency, and the performances of bit‐error‐rate (BER) and frame synchronization, with a highly simplified structure. Compared to the conventional frequency selective digital transmission supporting IEEE standard 802.15.6 for wireless body area networks, the proposed scheme improves the spectral efficiency from 0.25 bps/Hz to 1 bps/Hz based on the 3‐dB bandwidth of the transmit spectral mask, and the signal‐to‐noise‐ratio (SNR) by 0.51 dB at a BER of with an reduction in the detection complexity of the length of the Hamming distance computation. The proposed preamble structure using its customized detection algorithm achieves perfect frame synchronization at the SNR of a BER of by applying the proposed pre‐processing to compensate for the distortions on the preamble signals due to the band‐limit effects by transmit and receive filters.     

Stopband‐Extended and Size‐Miniaturized Low‐Pass Filter with Three Transmission Zeros

This paper presents a compact structure composed of an upper high‐impedance transmission line, a middle extended parallel coupled line, and a pair of inter‐coupled symmetrical stepped impedance stubs. Detailed investigation into this structure based on an equivalent circuit analysis reveals that this proposed structure exhibits a quasi‐elliptic low‐pass filtering response with three transmission zeros. Moreover, the positions of the three transmission zeros can be tuned and reallocated flexibly by choosing the proper circuit parameters. Finally, the design concept is validated through the design, fabrication, and measurement of two exemplary low‐pass filters (LPFs) with one single unit and two cascaded asymmetric units. The measured results agree well with the simulated results. In addition, in the range of 1.42 f_c to 7.03 f_c, the fabricated quasi‐elliptic LPFs experimentally demonstrate a very wide upper‐stopband of 20 dB using a compact size of only , where λ_g is the guided wavelength of a 50 Ω transmission line at the central frequency.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

Mixed‐Domain Adaptive Blind Correction of High‐Resolution Time‐Interleaved ADCs

Blind mismatch correction of time‐interleaved analog‐to‐digital converters (TI‐ADC) is a challenging task. We present a practical blind calibration technique for low‐computation, low‐complexity, and high‐resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI‐ADC channels and most real‐life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed‐domain error correction. The proposed technique is experimentally verified by an 400 MSPS TI‐ADC system. In a single‐tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.     

Low‐Power Channel‐Adaptive Reconfigurable 4×4 QRM‐MLD MIMO Detector

This paper presents a low‐complexity channel‐adaptive reconfigurable QR‐decomposition and M‐algorithm‐based maximum likelihood detection (QRM‐MLD) multiple‐input and multiple‐output (MIMO) detector. Two novel design approaches for low‐power QRM‐MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM‐MLD MIMO detector (where the M‐value represents the number of survival branches in a stage) for dynamically adapting to time‐varying channels is also proposed in this work. The proposed reconfigurable QRM‐MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM‐based QRM‐MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of MIMO with 64‐QAM. Under time‐varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.     

Supercapacitive Properties of Composite Electrode Consisting of Activated Carbon and Di(1‐aminopyrene)quinone

Di(1‐aminopyrene)quinone (DAQ) as a quinone‐containing conducting additive is synthesized from a solution reaction of 1‐aminopyrene and hydroquinone. To utilize the conductive property of DAQ and its compatibility with activated carbon, a composite electrode for a supercapacitor is also prepared by blending activated carbon and DAQ (3:1 w/w), and its supercapacitive properties are characterized based on the cyclic voltammetry and galvanostatic charge/discharge. As a result, the composite electrode adopting DAQ exhibits superior electrochemical properties, such as a higher specific capacitance of up to at , an excellent high‐rate capability of up to , and a higher cycling stability with a capacitance retention ratio of 82% for the 1,000th cycle.     

New Time‐Domain Decoder for Correcting both Errors and Erasures of Reed‐Solomon Codes

A new time‐domain decoder for Reed‐Solomon (RS) codes is proposed. Because this decoder can correct both errors and erasures without computing the erasure locator, errata locator, or errata evaluator polynomials, the computational complexity can be substantially reduced. Herein, to demonstrate this benefit, complexity comparisons between the proposed decoder and the Truong‐Jeng‐Hung and Lin‐Costello decoders are presented. These comparisons show that the proposed decoder consistently has lower computational requirements when correcting all combinations of ν errors and μ erasures than both of the related decoders under the condition of , where d_min denotes the minimum distance of the RS code. Finally, the (255, 223) and (63, 39) RS codes are used as examples for complexity comparisons under the upper bounded condition of . To decode the two RS codes, the new decoder can save about 40% additions and multiplications when as compared with the two related decoders. Furthermore, it can also save 50% of the required inverses for .     

Design of Multi‐time Programmable Memory for PMICs

In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.