Interconnection Technology Based on InSn Solder for Flexible Display Applications

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip‐chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.     

Curing Kinetics and Chemorheological Behavior of No‐flow Underfill for Sn/In/Bi Solder in Flexible Packaging Applications

A chemorheological analysis of a no‐flow underfill was conducted using curing kinetics through isothermal and dynamic differential scanning calorimetry, viscosity measurement, and solder (Sn/27In/54Bi, melting temperature of 86 °C) wetting observations. The analysis used an epoxy system with an anhydride curing agent and carboxyl fluxing capability to remove oxide on the surface of a metal filler. A curing kinetic of the no‐flow underfill with a processing temperature of 130 °C was successfully completed using phenomenological models such as autocatalytic and nth‐order models. Temperature‐dependent kinetic parameters were identified within a temperature range of 125 °C to 135 °C. The phenomenon of solder wetting was visually observed using an optical microscope, and the conversion and viscosity at the moment of solder wetting were quantitatively investigated. It is expected that the curing kinetics and rheological property of a no‐flow underfill can be adopted in arbitrary processing applications.     

Fine‐Pitch Solder on Pad Process for Microbump Interconnection

A cost‐effective and simple solder on pad (SoP) process is proposed for a fine‐pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60‐μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine‐pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine‐pitch SoP process and evaluate the fine‐pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45‐μm diameter and 60‐μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine‐pitch SoP and microbump interconnection using a screen printing process.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Flip Chip Assembly of Thinned Silicon Die on Flex Substrates

Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Conductive adhesive with transient liquid‐phase sintering technology for high‐power device applications

A highly reliable conductive adhesive obtained by transient liquid‐phase sintering (TLPS) technologies is studied for use in high‐power device packaging. TLPS involves the low‐temperature reaction of a low‐melting metal or alloy with a high‐melting metal or alloy to form a reacted metal matrix. For a TLPS material (consisting of Ag‐coated Cu, a Sn96.5‐Ag3.0‐Cu0.5 solder, and a volatile fluxing resin) used herein, the melting temperature of the metal matrix exceeds the bonding temperature. After bonding of the TLPS material, a unique melting peak of TLPS is observed at 356 °C, consistent with the transient behavior of Ag₃Sn + Cu₆Sn₅ → liquid + Cu₃Sn reported by the National Institute of Standards and Technology. The TLPS material shows superior thermal conductivity as compared with other commercially available Ag pastes under the same specimen preparation conditions. In conclusion, the TLPS material can be a promising candidate for a highly reliable conductive adhesive in power device packaging because remelting of the SAC305 solder, which is widely used in conventional power modules, is not observed.     

Highly reliable flip-chip-on-flex package using multilayered anisotropic conductive film

Anisotropic conductive film (ACF) has been used as interconnect material for flat-panel display module packages, such as liquid crystal displays (LCDs) in the technologies of tape automated bonding (TAB), chip-on-glass (COG), chip-on-film (COF), and chip-on-board (COB). Among them, COF is a relatively new technology after TAB and COG bonding, and its requirement for ACF becomes more stringent because of the need of high adhesion and fine-pitch interconnection. To meet these demands, strong interfacial adhesion between the ACF, substrate, and chip is a major issue. We have developed a multilayered ACF that has functional layers on both sides of a conventional ACF layer to improve the wetting properties of the resin on two-layer flex for better interface adhesion and to control the flow of conductive particles during thermocompression bonding and the resulting reliability of the interconnection using ACF. To investigate the enhancement of electrical properties and reliability of multilayered ACF in COF assemblies, we evaluated the performance in contact resistance and adhesion strength of a multilayered ACF and single-layered ACF under various environmental tests, such as a thermal cycling test (−55°C/+160°C, 1,000 cycles), a high-temperature humidity test (85°C/85% RH, 1,000 h), and a high-temperature storage test (150°C, 1,000 h). The contact resistance of the multilayered ACF joint was in an acceptable range of around a 10% increase of the initial value during the 85°C/85% RH test compared with the single-layered ACF because of the stronger moisture resistance of the multilayered ACF and flex substrate. The multilayered ACF has better adhesion properties compared with the conventional single-layered ACF during the 85°C/85% RH test because of the enhancement of the wetting to the surface of the polymide (PI) flex substrate with an adhesion-promoting nonconductive film (NCF) layer of multilayered ACF. The new ACF of the multilayered structure was successfully demonstrated in a fine-pitch COF module with a two-layer flex substrate.     

Assembly of lead-free bumped flip-chip with no-flow underfills

Lead-free solder reflow process has presented challenges to no-flow underfill material and assembly. The currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents the assembly of lead-free bumped flip-chip with developed no-flow underfill materials. Epoxy resin/HMPA/metal AcAc/Flux G system is developed as no-flow underfills for Sn/Ag/Cu alloy bumped flip-chips. The solder wetting test is conducted to demonstrate the fluxing capability of the underfills for lead-free solders. A 100% solder joint yield has been achieved using Sn/Ag/Cu bumped flip-chips in a no-flow process. A scanning acoustic microscope is used to observe the underfill voiding. The out-gassing of HMPA at high curing temperatures causes severe voiding inside the package. A differential scanning calorimeter (DSC) used to study the curing degree of the underfill after reflow with or without post-cure. The post-curing profiles indicate that the out-gassing of HMPA would destroy the stoichiometric balance between the epoxy and hardener, and result in a need for high temperature post-cure. The material properties of the underfills are characterized and the influence of underfill out-gassing on the assembly and material properties is investigated. The impact of lead-free reflow on the material design and process conditions of no-flow underfill is discussed.     

42Sn58Bi—96.5Sn3.5Ag系焊点疲劳性能的研究

本文研究了热处理时间对不同组分的４２Ｓｎ５８Ｂｉ－９６．５Ｓｎ３．５Ａｇ焊料疲劳性能的影响,研究发现适当的热处理时间能提高焊点的机械强度,延长焊点的疲劳寿命。     

Solder connections for high frequency applications between flexible and rigid printed circuit boards

This article examines the backplane connector technology for high frequency use and presents a novel concept for shielded enclosures without air vents. The experimental soldering of connections between a flexible printed circuit (flex, for short) and a FR4-board as part of a backplane connector is presented. A very high contact density is reached by soldering vias on the flex to pads on the FR4; this soldering was performed both with ordinary Sn/Pb solder material and as well with lead-free solder alloy. The solder joints were examined using a scanning electron microscope (SEM) and the electrical properties of the flex/solder joint structure were measured.     

Double bump flip-chip assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.     

Processing of fluxing underfills for flip chip-on-laminate assembly

Fluxing underfill eliminates process steps in the assembly of flip chip-on-laminate (FCOL) when compared to conventional capillary flow underfill processing. In the fluxing underfill process, the underfill is dispensed onto the board prior to die placement. During placement, the underfill flows in a "squeeze flow" process until the solder balls contact the pads on the board. The material properties, the dispense pattern and resulting shape, solder mask design pattern, placement force, placement speed, and hold time all impact the placement process and the potential for void formation. A design of experiments was used to optimize the placement process to minimize placement-induced voids. The major factor identified was board design, followed by placement acceleration. During the reflow cycle, the fluxing underfill provides the fluxing action required for good wetting and then cures by the end of the reflow cycle. With small, homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve good solder wetting. However, with complex SMT assemblies involving components with significant thermal mass this is more challenging.     

Study of the self-alignment of no-flow underfill for micro-BGA assembly

As a concept to achieve high throughput low cost flip-chip assembly, a process development activity is underway, implementing next generation flip-chip processing based on large area underfill printing/dispensing, IC placement, and simultaneous solder interconnect reflow and underfill cure. The self-alignment of micro-BGA (ball grid array, BGA) package using flux and two types of no-flow underfill is discussed in this paper. A “rapid ramp” temperature profile is optimized for reflow of micro-BGA using no-flow underfill for self-aligning and soldering. The effect of bonding force on the self-alignment is also described. A SOFTEX real time X-ray inspection system was used to inspect samples to ensure the correct misalignment before reflow, and determine the residual displacement of solder joints after reflow. Cross-sections of the micro-BGA samples are taken using scanning electronic microscope. Our experimental results show that the self-alignment of micro-BGA using flux is very good even though the initial misalignment was greater than 50% from the pad center. When using no-flow underfill, the self-alignment is inferior to that of using flux. However, for a misalignment of no larger than 25% from the pad center, the package is also able to self-align with S1 no-flow underfill. However, when the misalignment is 37.5–50% from the pad center, there are 10–14% residual displacement after reflow. The reason is the underfill resistant force inhibiting the self-alignment of the package due to rapid increment of underfill viscosity during reflow. The self-alignment of micro-BGA package using no-flow underfill allows only <25% misalignment prior to the soldering. During assembling, although the bonding force does not influence on the self-alignment of no-flow underfill, a threshold bonding force is necessary to make all solder balls contact with PCB pads, for good soldering. The no-flow underfill is necessary to modify the fluxing/curing chemistry for overcoming the effect of tin metal salt produced during soldering on underfill curing, and for maintaining the low viscosity during soldering to help self-alignment.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Interconnections based on Bi-coated SnAg solder balls

To decrease the bonding temperature required for eutectic SnAg solder, SnAg solder bumps were chemically coated with a pure Bi layer. During heating, a low melting eutectic forms between the Bi coating and the SnAg, enabling bonding at temperatures below the melting points of either pure Bi or SnAg solder. As the composition of the molten solder changes toward more dilute Bi concentrations, the melting point in the joint region increases and the joint solidifies. After solidification the joints will no longer melt at the original bonding temperature. Bi-coated SnAg solder balls were joined to metallized substrates at temperatures ranging from 180°C to 250°C. The microstructure at the joint interface was characterized by the SEM/EDS technique. As expected, at 180°C the Bi-coated SnAg solder balls melted only locally at the interfacial regions between the ball and the substrate and so retained their spherical shape during bonding. After solidification there were a lot of small Bi precipitates in the joint region. At higher temperatures, the wetting was evidently better, and there were less Bi precipitates, because the melt was more dilute in bismuth. In all cases, Bi formed relatively small, equi-axed precipitates instead of the eutectic structure found in eutectic Sn-Bi solder joints