The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Surface passivation of high‐efficiency silicon solar cells by atomic‐layer‐deposited Al2O3

Atomic‐layer‐deposited aluminium oxide (Al₂O₃) is applied as rear‐surface‐passivating dielectric layer to passivated emitter and rear cell (PERC)‐type crystalline silicon (c‐Si) solar cells. The excellent passivation of low‐resistivity p‐type silicon by the negative‐charge‐dielectric Al₂O₃ is confirmed on the device level by an independently confirmed energy conversion efficiency of 20·6%. The best results are obtained for a stack consisting of a 30 nm Al₂O₃ film covered by a 200 nm plasma‐enhanced‐chemical‐vapour‐deposited silicon oxide (SiO_x) layer, resulting in a rear surface recombination velocity (SRV) of 70 cm/s. Comparable results are obtained for a 130 nm single‐layer of Al₂O₃, resulting in a rear SRV of 90 cm/s. Copyright © 2008 John Wiley & Sons, Ltd.     

Role of ultrathin Al2O3 layer in organic/inorganic hybrid gate dielectrics for flexibility improvement of InGaZnO thin film transistors

We investigated flexible amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) on a polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and ultrathin Al₂O₃. IGZO TFTs were fabricated with hybrid PVP/Al₂O₃ gate dielectrics having Al₂O₃ layers of different nanoscale thicknesses, which were deposited by atomic layer deposition (ALD). The electrical characteristics of the TFTs with the organic/inorganic hybrid gate dielectrics were measured after cyclic bending up to 1,00,000 cycles at the bending radius of 10 mm. The ultrathin Al₂O₃ layer in the hybrid gate dielectrics improved the mechanical flexibility and protected the organic gate dielectric against damage during the sputter deposition of the IGZO layer. Finite elements method (FEM) simulations along with the structural characterization of the cyclically bent device showed the importance of optimizing the thickness of the Al₂O₃ layer in the hybrid gate dielectrics to obtain mechanically stable and flexible a-IGZO TFTs.     

Fabrication and characterization of Zr-rich Zr-aluminate films for high-κ gate dielectric applications

Two kinds of Zr-rich Zr-aluminate films for high-κ gate dielectric applications with the nominal composition of (ZrO₂)_0.8(Al₂O₃)_0.2 and (ZrO₂)_0.9(Al₂O₃)_0.1, were deposited on n-type silicon wafer by pulsed laser deposition (PLD) technique at different deposition conditions. X-ray diffraction (XRD) reveals that the (ZrO₂)_0.8(Al₂O₃)_0.2 film could remain amorphous after being rapid thermal annealed (RTA) at the temperature above 800 °C, while the other one displays some crystalline peaks at 700 °C. The energy gap calculated from optical transmittance spectrum of (ZrO₂)_0.8(Al₂O₃)_0.2 film on quartz is about 6.0 eV. Sputtering depth profile of X-ray photoelectron spectroscopy and Auger electron spectroscopy indicate that a Zr-Si-O interfacial layer was formed at the near surface of the silicon substrate. The dielectric constant of the (ZrO₂)_0.8(Al₂ O₃)_0.2 film has been determined to be 22.1 by measuring a Pt/(ZrO₂)_0.8(Al₂ O₃)_0.2/Pt MIM structure. An EOT of 1.76 nm with a leakage current density of 51.5 mA/cm² at 1 V gate voltage for the film deposited in N₂ were obtained. Two different pre-treatments of Si substrates prior to depositions were also carried out and compared. The results indicate that a surface-nitrided Si substrate can lead to a lower leakage current density. The amorphous Zr-rich Zr-aluminate films fabricated by PLD have promising structure and dielectric properties required for a candidate material for high-κ gate dielectric applications.     

Atomic-layer-deposited Al2O3 and HfO2 on GaN: A comparative study on interfaces and electrical characteristics

Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ films were deposited on n-type GaN using atomic layer deposition (ALD). The interfacial layer of GaON and HfON was observed between HfO₂ and GaN, whereas the absence of an interfacial layer at Al₂O₃/GaN was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The dielectric constants of Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ calculated from the C-V measurement are 9, 16.5, and 13.8, respectively. The Al₂O₃ employed as a template in the composite structure has suppressed the interfacial layer formation during the subsequent ALD-HfO₂ and effectively reduced the gate leakage current. While the dielectric constant of the composite HfO₂/Al₂O₃ film is lower than that of HfO₂, the composite structure provides sharp oxide/GaN interface without interfacial layer, leading to better electrical properties.     

Leakage current in single electron device due to implanted gallium dopants by focus ion beam

Focus ion beam (FIB) technology has been employed to fabricate quantum dot based devices such as the single electron transistor (SET) on a silicon substrate with Cr/Au/Al₂O₃ film stack. It was discovered that the dwell time of FIB gallium beam on an area impacted the dosage of gallium ions implanted into the insulating substrate, creating a highly doped region which could lead to device leakage current. This work focus on the potential electron transport possible when an over-dosed gallium rich Al₂O₃ layer will lead to leakage current between otherwise electrically isolated contact pads. Using the Keithley 4200 semiconductor parametric analyzer (SPA) and the energy dispersive X-ray spectrometer (EDS) analysis; we demonstrate the detrimental effect of leakage current in the range of pA, observed between drain/source electrodes due to the high dose of gallium implanted into the insulating Al₂O₃. The optimized FIB etching parameters to produce a high quality of device functionality with no leakage current is also demonstrated.     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

Patterning effects on poly (3-hexylthiophene) organic thin film transistors using photolithographic processes

We explore the effects of conventional photo lithographic patterning of the active layer of poly (3-hexylthiophene) (P3HT) organic thin film transistors (OTFT) on device performance. The performance of the devices was monitored in each step of the patterning process. We successfully developed a patterning process which is compatible with plastic substrates and P3HT as the organic semiconductor. In this process, parylene and atomic layer deposition (ALD) Al₂O₃ were used as capping layers. Al₂O₃ and parylene/P3HT were etched using Al etchant and O₂ plasma reactive ion etching (RIE), respectively. The degradation occurred primarily during the ALD Al₂O₃ deposition and capping layer etching. There was a 30% degradation in mobility, a 1–2× reduction in drive current, and an increase in threshold voltage after the ALD Al₂O₃ deposition. In the capping layer etching, a near 50% degradation in mobility was observed. The patterned devices have a mobility of 0.02 cm²/V s, which is 1000× better than photo lithographically patterned P3HT OTFTs previously reported in the literature, and comparable to un-patterned P3HT devices.     

Amorphous Boron Nitride: A Universal,Ultrathin Dielectric For 2D Nanoelectronics

Next‐generation nanoelectronics based on 2D materials ideally will require reliable, flexible, transparent, and versatile dielectrics for transistor gate barriers, environmental passivation layers, capacitor spacers, and other device elements. Ultrathin amorphous boron nitride of thicknesses from 2 to 17 nm, described in this work, may offer these attributes, as the material is demonstrated to be universal in structure and stoichiometric chemistry on numerous substrates including flexible polydimethylsiloxane, amorphous silicon dioxide, crystalline Al₂O₃, other 2D materials including graphene, 2D MoS₂, and conducting metals and metal foils. The versatile, large area pulsed laser deposition growth technique is performed at temperatures less than 200 °C and without modifying processing conditions, allowing for seamless integration into 2D device architectures. A device‐scale dielectric constant of 5.9 ± 0.65 at 1 kHz, breakdown voltage of 9.8 ± 1.0 MV cm^?1, and bandgap of 4.5 eV were measured for various thicknesses of the ultrathin a‐BN material, representing values higher than previously reported chemical vapor deposited h‐BN and nearing single crystal h‐BN.     

Optoelectronic In‐Ga‐Zn‐O Memtransistors for Artificial Vision System

An artificial vision system that can simulate the visual functions of human eyes is required for biological robots. Here, In‐Ga‐Zn‐O memtransistors using a naturally oxidized Al₂O₃ and an ion gel as a common gate stacking dielectric is proposed. Positive charge trapping in the Al₂O₃ layer can be induced by modulating the gate voltage, which causes the back sweep subthreshold swing (SS) of the device to break the physical limit (≥60 mV per decade at room temperature), and the minimum SS is as low as 26.4 mV per decade. In addition, photogenerated charges in the device are captured at the In‐Ga‐Zn‐O channel/ion gel interface due to the superposition of the additional electric field generated by positive charges trapped in the Al₂O₃ layer and the external gate electric field. Thus, persistent photoconductivity is observed in the In‐Ga‐Zn‐O memtransistors. Finally, by employing the optoelectronic memristive functions of In‐Ga‐Zn‐O memtransistors, an artificial vision system based on artificial retinal array (ARA) and artificial neural network is proposed. An obvious improvement in the recognition rate and efficiency with the use of ARA for the image preprocessing is achieved. This study provides a new strategy for the realization of artificial vision systems.     

Atomic Layer Deposition in the Production of a Gate HkMG Stack Structure with a Minimum Topological Size of 32 nm

The plasma-enhanced atomic layer deposition (PEALD) of a High-K Dielectric and Metal Gate (HkMG) stack for MIS transistors, including the subgate HfO₂ (2–4 nm) dielectric layer, the ultrathin metallic stabilizing hafnium nitride HfN (1–3 nm) layer, and the basic metallic gate layer from tantalum nitride ТаN (10–20 nm), on silicon plates with a diameter of 200 mm is studied. The spectral ellipsometry method is applied to measure the homogeneity of the deposited film thickness. The dielectric constant of the dielectric in the stack, the leak current, and the breakdown voltage are examined. The four-probe method is used to study the specific electric resistance of tantalum nitride deposited by the atomic layer deposition ALD method. The film thickness homogeneity as a function of the ALD process parameters is examined. The specific resistance of the metallic TaN layer as a function of the composition and parameters of the plasma discharge are studied.     

Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al₂O₃ gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm²/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

Superior suppression of gate current leakage in Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/Si<Subscript>3</Subscript>N<Subscript>4</Subscript> bilayer-based AlGaN/GaN insulated gate heterostructure field-effect transistors

AlGaN/GaN-based metal-insulator-semiconductor heterostructure field-effect transistors (MIS-HFETs) with Al₂O₃/Si₃N₄ bilayer as insulator have been investigated in detail, and compared with the conventional HFET and Si₃N₄-based MIS-HFET devices. Al₂O₃/Si₃N₄ bilayer-based MIS-HFETs exhibited much lower gate current leakage than conventional HFET and Si₃N₄-based MIS devices under reverse gate bias, and leakage as low as 1×10⁻¹¹ A/mm at −15 V has been achieved in Al₂O₃/Si₃N₄-based MIS devices. By using ultrathin Al₂O₃/Si₃N₄ bilayer, very high maximum transconductance of more than 180 mS/mm with ultra-low gate leakage has been obtained in the MIS-HFET device with gate length of 1.5 μm, a reduction less than 5% in maximum transconductance compared with the conventional HFET device. This value was much smaller than the more than 30% reduction in the Si₃N₄-based MIS device, due to the employment of ultra-thin bilayer with large dielectric constant and the large conduction band offset between Al₂O₃ and nitrides. This work demonstrates that Al₂O₃/Si₃N₄ bilayer insulator is a superior candidate for nitrides-based MIS-HFET devices.     

Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO₂ were studied. It is shown that compared with a conventional Al₂O₃–HfO₂–Al₂O₃ high–low–high barrier structure, the HfO₂–Al₂O₃–HfO₂ multilayer IPD stack with a low–high–low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high-κ IPD.     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

Incorporation of dielectric layers into the processing of III-nitride-based heterostructure field-effect transistors

Dielectric layers within III-nitride transistor technology can act either as passivation layers or as gate-dielectric layers. In this paper, we reflect on both issues and present novel approaches of dielectric schemes. In both cases, the elimination of surface traps or, more generally, of surface states is a key issue in obtaining improved device performance. As gate dielectrics, we introduced and investigated thermally and photoelectrochemically generated Al_xGa_2−xO₃, SiO₂, the combination of Al_xGa_2−xO₃ and SiO₂ (tandem-dielectric stack), and e-beam-deposited Al₂O₃. These dielectric layers serve simultaneously as a passivation layer. In addition, we introduced plasma-enhanced chemical-vapor deposition (PECVD)-deposited SiN_x for passivation. The results highlight the importance of passivation and the introduction of gate dielectrics and emphasize the relationship between surface states and improved direct-current (DC) performance. Backed by additional measurements, we proposed a different gateleakage mechanism for heterostructure field-effect transistor (HFET) and metal-oxide semiconductor heterostructure field-effect transistor (MOSHFET) devices.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

电子束辐照下的石墨烯上的原子层沉积Al2O3介质层

为了研究石墨烯与高k介质的结合,使用原子层沉积氧化铝在石墨衬底上。沉积前使用电子束辐照,观测到了氧化铝明显改善的形貌。归因于电子束辐照过程中的石墨层的无定形变化过程。     

The electrical and physical analysis of Pt gate/Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

In order to examine the electrical and physical properties of Al₂O₃ layers with dual thickness on a chip, Pt gate/Al₂O₃ with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al₂O₃ layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al₂O₃ layers showed a good leakage current density of −5.4×10⁻⁶ A/cm² and −2.5×10⁻⁹ A/cm² at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×10¹⁰ cm⁻²eV⁻¹ near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al₂O₃ layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al₂O₃ layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al₂O₃ layer and high reliability regions with a thick Al₂O₃ layer.