Test structures for MCM-D technology characterization

In this paper we present a set of classic and novel test structures addressed to fully characterize multichip module (MCM) technologies. The structures have been implemented and fabricated in our D-type, flip-chip, ball grid array, silicon substrate technology. In this technology, a silicon chip is used as a substrate on which other commercial chips are flipped and soldered by a screen-printing method. These complex technologies have specific test problems that are solved with this approach. We have specially focused on the measurement of the effects of wafer rerouting on CMOS parameters, the chip-to-chip ball contact resistance, thermal behavior, yield, and reliability of the technology. Experimental results are shown, proving that this methodology is suitable for our technology and can also be applied to other different MCM technologies     

SnAg Microbumps for MEMS-Based 3-D Stacks

Fine pitch 100-$mu{rm m}$ electroplated SnAg microbump interconnection technology is presented and discussed for use in microelectromechanical systems (MEMS) based 3-D stacks. Electrochemical deposition (ECD) of copper top side metallization (TSM) is compared to performance of nickel–copper TSM on substrate chips. Nickel–copper was selected for under bump metallization (UBM) of die chips. Lead free Sn3.5%Ag was deposited on the die chip UBM and chip-to-wafer bonded by a standard SnAg reflow process in inert atmosphere. An automotive application module was selected as target application for investigating reliability and failure mechanism of the interconnection technology. Bonded units have been investigated by mechanical and physical analysis, visual inspection and electrical resistance measurements after assembly and subsequent environmental stress test including thermal cycling, elevated temperature, humidity, and high current. The fine pitch lead free microbumps displayed promising capability for 3-D stacking of silicon devices. Excellent performance under thermal cycling with no global thermal mismatch was demonstrated. The microbump interconnection technology proved to be tolerant to high temperature and extensive current exposure. TSM consumption and intermetallic compound (IMC) formation were less evident for the nickel–copper TSMs compared to those entirely made of copper. Only minor Kirkendall porosity was observed at the solder alloy interfaces in the present study.      

硅通孔互连技术的可靠性研究

随着电子封装持续向小型化、高性能的方向发展,基于硅通孔的三维互连技术已经开始应用到闪存、图像传感器的制造中,硅通孔互连技术的可靠性问题越来越受到人们的关注。将硅通孔互连器件组装到PCB基板上,参照JEDEC电子封装可靠性试验的相关标准,通过温度循环试验、跌落试验和三个不同等级的湿度敏感性测试研究了硅通孔互连器件的可靠性。互连器件在温度循环试验和二、三级湿度敏感试验中表现出很好的可靠性,但部分样品在跌落试验和一级湿度敏感性测试中出现了失效。通过切片试验和扫描电子显微镜分析了器件失效机理并讨论了底部填充料对硅通孔互连器件可靠性的影响。     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Boundary element analysis of thermal fatigue effects on high power IGBT modules

The technology of high power IGBT modules has been significantly improved these last years against thermal fatigue. The most frequently observed failure modes, due to thermal fatigue, are the solder cracks between the copper base plate and the direct copper bonding (DCB) substrate and bond wire lift-off. Specific simulation tools are needed to carry out reliability researches and to develop device lifetime models. In other respects, accurate temperature and flux distributions are essential when computing thermo-mechanical stresses in order to assess the lifetime of high power modules in real operating conditions. This study presents an analysis method based on the boundary element method (BEM) to investigate thermal behavior of high power semiconductor packages subjected to power cycling loads. The paper describes the boundary integral equation which has been solved using the BEM and applied to the case of a high power IGBT module package (3.3 kV–1.2 kA). A validation of the numerical tool is presented by comparison with experimental measurements. Finally, the paper points out the effect on the thermal stress of the IGBT chips position on the DCB substrate. In particular, a light shifting of the silicon chips may be sufficient to delay significantly the initiation and the propagation of the cracks, allowing a higher device lifetime of the studied module.     

Wafer-chip assembly for large-scale integration

A technique has been developed for achieving a very high density interconnection of active silicon devices to permit the fabrication of large electronic subsystems in essentially monolithic form. The technique has been used to assemble a MOS 2000-bit shift register containing 12 000 MOS transistors on a 300 by 600 mils silicon substrate. The register utilizes ten 200-bit shift-register chips, each containing 1200 transistors. Four-phase MOS logic techniques are used to obtain very low power (0.1 mW/bit) and/or high frequency (10 MHZ) operation. In the technique used to assemble the 2000-bit shift register, silicon large-scale array chips are face-down bonded in adjoining positions on a larger silicon wafer section which may contain additional layers of interconnections and/or active devices as required to form a complete system subassembly. Since the same photoengraving technology is used in the substrate as on the chips, very high packing densities can be achieved, with minimum chip area required for interconnections. This approach also minimizes the parasitic capacitance associated with more conventional techniques for encapsulating and interconnecting large-scale arrays. In the case of MOS circuits, large area-buffer devices are not needed due to the small capacitance in the wafer-chip interconnections. Various techniques have been evolved for processing the chips and substrates produce contact regions which permit the required high fabrication yields. The bonding conditions and metallurgical systems used to date in fabricating large shift-register assemblies will be described and compared with other approaches.     

Reliability and lifetime evaluation of different wire bonding technologies for high power IGBT modules

IGBT modules for power transmission, industrial and traction applications are operated under severe working conditions and in harsh environments. Therefore, a consequent design, focused on quality, performance and reliability is essential in order to satisfy the high customer requirements. One of the main failure mechanisms encountered in high power IGBT modules subjected to thermal cycles is wire bond lift-off, which is due to the large thermal expansion coefficient mismatch between the aluminum wires and the silicon chips. The paper describes various bonding technologies using different wire materials directly bonded onto chip metallisation as well as the ABB solution where the wire is bonded on a thin molybdenum strain buffer soldered onto the chip. We assess in the present paper the potential of these technologies to enhance module reliability and lifetime through a power cycling test. Failure analysis results are presented and the failure mechanisms related to each technology are explained in detail.     

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.     

Stacked solder bumping technology for improved solder joint reliability

Solder joint failure is a serious reliability concern in flip-chip and ball grid array packages of integrated-circuit chips. In current industrial practice, the solder joints take on the shape of a spherical segment. Mathematical calculations and finite element modeling have shown that hourglass-shaped solder joints would have the lowest plastic strain and stress during a temperature cycle, thus the longest lifetime. In an effort to improve solder joint reliability, we have developed a stacked solder bumping technique for fabricating triple-stacked hourglass-shaped solder joints. This solder bumping technology can easily control the solder joint shape and height. The structure of triple-stacked solder joints consists of an inner cap, middle ball and outer cap. The triple-stacked solder joints are expected to have greater compliance than conventional solder joints and are able to relax the stresses caused by the coefficient of thermal expansion mismatching between the silicon chips and substrates since it has a greater height. Furthermore, the hourglass-shaped solder joints are to have a much lower stress/strain concentration at the interface between the solder joint and the silicon die as well as at the interface between the solder joint and substrate than barrel-shaped solder joints, especially around the corners of the interfaces. In this paper, the solder bumping process is designed and joint reliability is evaluated. Mechanical tests have been carried out to characterize the adhesion strength of the solder joints. The interfaces of the solder joints are investigated by scanning electron microscopy and energy dispersive X-ray analysis. Temperature cycling results show that the triple-stacked hourglass-shaped solder joints are more reliable than the traditional spherical-shaped solder joints.     

A BiCMOS active substrate probe-card technology for digital testing

An active substrate silicon probe card has been implemented by forming a polyimide membrane on a silicon substrate. The probe card combines tungsten probe tips and aluminum interconnects in the polyimide membrane with active test circuitry integrated in the substrate. A monolithic prototype of the probe card designed to enhance the capabilities of conventional digital test systems has been fabricated in a 2-μm BiCMOS technology. The benefits of the proposed probe-card technology could be further exploited by integrating the timing measurement unit of a digital tester into the probe-card substrate. An integrated tester architecture based on time digitization is described. A prototype of a tester combining a time digitizer and two test channels has been integrated in a 0.6 μm BiCMOS technology. The time digitizer in the experimental circuit employs a two-stage ring oscillator that is phase-locked to an external reference and makes use of phase interpolation to achieve a timing resolution of 90 ps     

Reliability challenges of automotive power electronics

A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface – the chip solder layer – can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder-free module shows an improved performance in passive and active cycling tests.     

应用于柔性电子的超薄硅基芯片研究进展北大核心

柔性电子技术在近些年得到了快速发展，越来越多的柔性电子系统需要柔性、高性能的集成电路来实现数据处理和通信。通过减薄硅基芯片可以获得高性能的柔性集成电路，但是硅基芯片减薄之后的性能有可能发生变化，并且在制备、转移、封装的过程中极易产生缺陷或者破碎，导致芯片性能退化甚至失效。因此，超薄硅基芯片的制备工艺和柔性封装技术对于制备高可靠性的柔性硅基芯片十分关键。在此背景下，文章综述了柔性硅基芯片的力学和电学特性研究进展，介绍了几种超薄硅基芯片的减薄工艺和柔性封装前沿技术，并对超薄硅基芯片在柔性电子领域的应用和发展进行了总结和展望，为柔性硅基芯片技术的进一步研究提供参考。     

MCM-D技术电热特性综述

本文主要说明了淀积型多芯片组件(MCM-D)技术所使用的主要材料的热特性。此技术采用倒装片技术把硅芯片安装到硅基板上。阐述了薄膜电阻和接触电阻的测量与所使用金属的温度范围-28℃-100℃的比较。一套典型的试验结构诸如开尔文接触、横桥电阻(CBR)及Van der Pauw 结构不仅已用于此技术,而且为了测试通过球倒装片连接的接触电阻,采用一新的开尔文式结构。已获得MCM封装的热模型,并考虑由此类封装增加的所有的热电阻。     

Optimization of Thermomechanical Reliability of Board-Level Flip-Chip Packages Implemented With Organic or Silicon Substrates

A design that optimizes package-level along with board-level thermomechanical reliability of a flip-chip package implemented with an organic or a silicon substrate is provided for the package subjected to an accelerated thermal cycling test condition. Different control factors including thickness of substrate, die, board, and polyimide or soldermask are considered. The optimal design is obtained using an L₉ (3⁴) orthogonal array according to the Taguchi optimization method. Importance of each of these control factors is also ranked.     

Reliability of adhesive joined thinned chips on flexible substrates under humid conditions

Thin chips are an interesting option for reducing the thickness of an electronics package. In addition to the reduced size, thinned chips are flexible and can dissipate more heat than thicker ones. Joining of the thin chips can be done using several different techniques. Of these, anisotropic conductive adhesives (ACA) are an interesting option as they have several advantages, such as low bonding temperature and capability for high density interconnections. The reliability of ACA flip chip joints under thermal cycling conditions has been found to increase when thinned chips are used. However, the effect of humidity has not been fully explored. In this study the reliability of thinned chips (50 μm) under humid conditions was investigated using thin flexible substrates. Seven test lots were assembled with thinned chips using two different ACA films and liquid crystal polymer (LCP), polyimide (PI) and thin FR-4 substrates. A high humidity and high temperature test was used to study the reliability of the interconnections. A finite element model (FEM) was used to analyse the stresses in the test samples during testing. Several failures occurred during the test and significant differences between the substrates were seen. Additionally, bonding pressure was found to be a critical factor for the reliability under the humid conditions.     

Extensive electrical and thermal characterization of an MCM-Dtechnology

In this paper, it is shown the work carried out on thermal characterization of the main materials employed in the deposited-type multichip module (MCM-D) technology. In this technology, silicon chips are mounted onto a silicon substrate by a flipchip technique. The substrates can be either passive with interconnection lines, Rs, Cs, and Ls or active with complementary metal oxide semiconductor (CMOS) technology cells. The metals used in this technology are aluminum for interconnection purposes, tantalum silicide for making resistors and a multilayer of wettable metal for solder connection. Measurements of sheet resistance and contact resistance versus temperature in the range of -28°C to 100°C of the metals used in the technology are shown. A set of classic test structures such as Kelvin contacts, cross bridge resistors (CBR), and Van der Pauw structures have been used for this purpose as well as a new Kelvin-like structure to test the contact resistance of the Flip Chip connection through the ball. This structure has been proven to be very sensitive allowing the measurement of changes in ball resistance in the range of mΩ. A thermal model of the MCM package has been obtained, taking into account all the thermal resistances added by this kind of package     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Development of 3-D Stack Package Using Silicon Interposer for High-Power Application

Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3-D stacked package with silicon interposers was developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer were formed by through silicon via. Silicon interposer has much high thermal conductivity than organic interposer, therefore the package thermal resistance is lower. Thermal performances of the 3-D package were analyzed and thermal enhancements like thermal via, thermal bridging were evaluated. The designed package showed 5 times lesser thermal resistance compared to a similar package with organic substrate. An additional silicon heat spreader was designed and attached to the package for high power application. Thermal analysis was performed to optimize package thermal performances and experimental validation was carried out. The designed 3-D stack package is suitable for 20 W application.     

基于边界扫描的逻辑簇测试诊断软件开发

在边界扫描测试技术中,由非BS器件组成的逻辑簇的测试是难点问题。介绍了一种逻辑簇测试诊断软件的原理、过程和应用,并通过实例验证了其有效性与可靠性。