基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

基于FPGA的RS码译码器的设计

介绍了符合CCSDS标准的RS(255,223)码译码器的硬件实现结构。译码器采用8位并行时域译码算法,主要包括了修正后的无逆BM迭代译码算法,钱搜索算法和Forney算法。采用了三级流水线结构实现,减小了译码器的时延,提高了译码的速率,使用了VHDL语言完成译码器的设计与实现。测试表明,该译码器性能优良,适用于高速通信。     

一种基于ME算法的RS译码器VLSI高速实现方法

针对ME算法VLSI结构进行了分析,提出ME算法的流水线及最小化VLSI结构,以满足数据处理速率不断提高的需求。并利用该算法实现结构设计了一种低资源占用率、低成本的高速RS译码器。逻辑综合及仿真结果表明,基于Altera公司CycloneII系列FPGA的RS(255,239)译码器,工作时钟达210 MHz,可满足数据速率1.68 Gb·s^-1的编译码要求。     

符合CCSDS标准的RS(255,223)译码器算法与FPGA实现

介绍了符合CCSDS标准的RS(255,223)码的参数与译码器结构,给出了一种改进型无逆BM算法用于求解关键方程,使用Verilog语言完成了基于该算法的译码器设计与实现.测试结果表明,该译码系统性能优良,在尽可能节约硬件资源的同时满足了高速处理的需要.     

变参数RS译码器IP核的实现

设计出一种码长可以变化的RS码译码器IP核电路,可进行RS(15,5)、RS(15,7)、RS(15,9)以及RS(15,11)的译码。译码器电路使用BM迭代译码算法,并在硬件电路中加以改进,使得电路能扩充到编译纠错位数多的复杂RS码。该译码器电路尽可能多地使用可以共享的模块,降低了电路的规模。硬件电路采用V erilogHDL进行描述,并在FPGA上进行了验证,同时给出了硬件电路在逻辑分析仪上得到的结果。     

动态自适应低密度奇偶校验码译码器的FPGA实现

在复杂深空通信环境中,自适应能力的强弱对低密度奇偶校验(LDPC)码译码器能否保持长期稳定工作具有重要影响。该文通过对DVB-S2标准LDPC码译码器各功能模块的IP化设计,将动态自适应理论参数化映射到各功能模块中,实现动态自适应LDPC码译码器的设计。基于Stratix IV系列FPGA的验证结果表明,动态自适应LDPC译码器可以满足不同码率码长及不同性能需求下的译码。同时,单译码通道可以保证译码数据信息吞吐率达到40.9~71.7 Mbps。     

T-MMB系统中LDPC码译码器的FPGA设计与实现

本文设计了一种符合手机电视T-MMB标准的信道译码解决方案,并进行了MATLAB仿真和FPGA的实现。同时针对部分并行结构的准循环低密度校验(QC-LDPC)码译码器,提出了基于块RAM的高效存储方法。该方法既可以同时读取用于运算的校验节点信息或变量节点信息,又可以实现在同一块RAM中存储不同子矩阵对应的校验节点信息或变量节点信息,不仅避免了块RAM资源的浪费,而且减少了译码器实现所需的存储资源数量。在Xilinx公司Virtex-4系列的FPGA上的实现结果表明,与传统的子矩阵与块RAM一对一存储的译码结构相比,本文提出的QC-LDPC码译码器设计方法能够在减少块RAM数量的同时有效地提高系统的时钟频率和译码吞吐量。     

DVB-H中高效低延迟RS译码器的设计

针对DVB-H中RS(255,191)码译码器消耗硬件多、延迟时间长等缺点,通过采用脉动式阵列及新的修正Euclidean迭代算法实现结构,并用查找表ROM取代常规求逆电路,设计了一种高效低延迟的RS(255,191)译码器.该译码器符合DVB-H标准的性能要求,同时缩小了电路规模,缩短了译码延迟时问.     

基于RiBM算法的RS译码器设计和实现

根据某无线光通信系统的需求,提出了一种基于BM算法的RS(255,239)的硬件译码器,并完成了该译码器的设计和实现;译码器采用流水线算法实现,其中关键方程求解模块采用修正的无逆BM算法.测试结果表明,该译码系统性能优良,在尽可能节约硬件资源的同时满足了高速处理的需要.     

Design of High‐Speed CAVLC Decoder Architecture for H.264/AVC

In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.     

A Universal VLSI Architecture for Reed–Solomon Error-and-Erasure Decoders

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mum 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm² silicon area, and the average core power consumption is 68.1 mW.     

Concurrent Error Detection in Reed–Solomon Encoders and Decoders

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2^m). These properties are related to the parity of the binary representation of the elements of the Galois field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented.     

一种高速Viterbi译码器幸存路径管理模块的改进结构

针对高速Viterbi译码器的高速,低延迟,低电路复杂度的要求,在分段执行的Hybrid Trace Forward方法的基础上,提出了一种新的幸存路径管理模块(SMU)结构—固定段长的结构。对于(m,n,k)的Viterbi译码器,约束长度为k,则固定段长为k-1,既节省了存储空间,又消除了回溯过程,从而降低了延迟时间和电路复杂度。文中设计了一个(2,1,7)Viterbi译码器的SMU模块,采用固定长度为6的结构。相比于传统的分段执行的Hybrid Trace Forward结构,译码延迟减小了17%,输出数据间隔减小了33%,并且省去了存储器的使用。     

Filterbank Decompositions for (Non)-Systematic Reed–Solomon Codes With Applications to Soft Decoding

This paper focuses on Reed-Solomon (RS) codes, which are the most widespread classical error correcting codes. Recently, we have shown that an finite-impulse response (FIR) critically subsampled filterbank representation can be derived for some RS codes. However, this work only addresses RS codes with a non-coprime codeword and dataword length, seriously limiting its practical usability. In this paper, an alternative purely algebraic method is presented to construct such a filterbank. Apart from providing additional insight into the algebraic structure of (non-systematic) RS codes, this method is suited to eliminate the non-coprimeness constraint mentioned before. Using this filterbank decomposition, a RS code is broken into smaller subcodes that can subsequently be used to build a soft-in soft-out (SISO) RS decoder. It is shown how any RS code, written as an FIR filterbank, can be SISO decoded using the filterbank based decoder. Owing to the importance of systematic RS codes, it is shown that any systematic RS code can be decoded using the FIR filterbank decomposition. This leads to better decoding performance in addition with a slightly lower complexity. A further extension towards systematic RS codes is also presented in this paper resulting in an infinite-impulse response critically subsampled filterbank representation.     

Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

Non-binary low density parity check (NB-LDPC) codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios (SNR) are required. They have better burst error correcting performance, especially with high order Galois fields (GF). A shared comparator(SCOMP) architecture for elementary of check node (ECN)/elementary of variable node (EVN) to reduce decoder complexity is introduced because high complexity of check node (CN) and variable node (VN) prevent NB-LDPC decoder from widely applications. The decoder over GF(16) is based on the extended min-sum (EMS) algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency,the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when shared comparator architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF(64) or GF(256). Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.     

Multiple-symbol parallel decoding for variable length codes

In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.     

A high-speed low-complexity Reed-Solomon decoder for optical communications

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.     

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

This paper proposes a high-speed and area-efficient three-parallel Reed-Solomon (RS) decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve a high throughput rate, the inner signals, such as the syndrome, error locator and error value polynomials, are computed in parallel. In addition, the key equations are solved by using the S-DCME algorithm to reduce the hardware complexity. To handle the many problems caused by applying the S-DCME algorithm to the KES block, we modify the architectures of some of the blocks in the three-parallel RS decoder. The proposed RS architecture can reduce the hardware complexity by about 80% with respect to the KES block. In addition, the proposed RS architecture has an approximately 25% shorter latency than the conventional parallel RS architectures.     

Variable shortened-and-punctured Reed-Solomon codes for packet loss protection

Techniques using Reed-Solomon (RS) codes to recover lost packets in digital video/audio broadcasting and packet switched network communications are reviewed. Usually, different RS codes and their corresponding encoders/decoders are designed and utilized to meet different requirements for different systems and applications. We incorporate these techniques into a variable RS code and present encoding and decoding algorithms suitable for the variable RS code. A mother RS code can be used to produce a variety of RS codes and the same encoder/decoder can be used for all the derivative codes, with adding/detecting zeros, removing some parity symbols and adding erasures. A VLSI implementation for erasure decoding of the variable RS code is described and the achievable performance is quantitatively analyzed. A typical example shows that the signal processing speed is up to 2.5 Gbits/second and the processing delay is less than one millisecond, when integrating the decoder on a single chip. Therefore, the proposed algorithm and the encoder/decoder can universally be utilized for different applications with various requirements, such as transmission data rate, packet length, packet loss protection capacity, as well as layered protection and adaptive redundancy protection in DVB/DAB, Internet and mobile Internet communications.