LADA涂胶轨道的改造与实用化生产

1　前言ＬＡＤＡ涂胶轨道硅片处理系统从1997年5月16日开始安装调试。在调试过程中,经过光刻工艺人员进行了大量的工艺实验,维修人员则根据调试过程中设备暴露出的问题做了很多改造工作,经过验收,投入了正常的使用。这其中主要解决的问题是:(1)提高涂胶的均匀性(2)解决涂胶过程中的回溅现象(3)实际流片验证2　设备介绍ＬＡＤＡ涂胶轨道的基本结构示意图如图1。图1　ＬＡＤＡ涂胶轨道基本结构示意图　　ＷＬ、ＷＲ分别为硅片发送和接收模块;ＨＰ1、ＨＰ2为热板模块;ＴＳ为温度稳定模块;ＰＨＣ为涂胶模块;ＴＲ为硅片传送模块。该设备由计算机…     

全自动涂胶设备及涂胶工艺的研究

涂胶作为光刻工艺的重要环节,为了保证涂胶工艺质量,提高涂胶设备的自动化程度,减少中间污染环节,开发了一种全自动涂胶设备,通过对涂胶腔体和机械手等关键部件的改进,更好地满足了用户生产线要求;并通过对涂胶工艺中影响膜厚均匀性的重要因素进行研究、实验和分析,得出了适合用户生产线的工艺配方。     

浅谈半导体涂胶显影设备生产的洁净度控制

在半导体生产过程中,若生产设备存在杂质污染物会改变或破坏半导体的特性,因此,必须对杂质污染物进行严格控制。基于半导体制造厂对半导体涂胶显影设备中的污染颗粒要求,对半导体涂胶显影设备的零部件清洁过程、装配过程、调试过程、包装过程等环节污染颗粒管控进行介绍,对半导体涂胶显影设备中污染颗粒超标的常见问题进行分析,并提出污染颗粒的把控方法,以期为相关人员提供参考。     

底部填充技术的SMT应用研究

如BGA、CSP等倒装芯片的SMT应用越来越普遍,底部填充胶水可以有效提高倒装芯片焊点的机械强度,以避免因热循环应力疲劳或机械冲击力而产生的失效。本文详细描述了底部填充技术的SMT应用细节,包括底部填充胶水介绍、PCB DFM设计、涂胶前准备、涂胶过程和注意事项、涂胶设备介绍等。     

光刻胶涂胶厚度均匀性影响因素探究

介绍了光刻胶涂胶过程中对涂胶厚度均匀性的影响因素及发生均匀性问题的成因。对光刻工艺和光刻胶进行概述,通过对光刻工艺和光刻胶的涂胶学习可发现随着光刻工艺的不断进步,对光刻胶涂胶胶厚均匀性要求也在不断地提升,在实际的生产过程中却经常会出现涂胶均匀性较差而无法满足工艺要求。重点针对光刻胶涂胶厚度均匀性影响因素进行探究,详细介绍了会对其产生影响的因素。通过有效地管控好这些影响因素能够确保涂胶厚度均匀性,提升曝光质量,从而推动光刻技术的发展。     

彩色PDP封接涂胶设备研制

详细介绍了彩色PDP封接涂胶设备的研制过程及其工作原理、起始段均匀性处理、系统功能、软件设计等相关技术。     

EVG集团在“SEMICON中国2004”博览会上介绍新产品

为全球提供圆片键合设备和光刻设备的EVG集团在不久前举行的“SEMICON中国2004”博览会上介绍了该公司最新一代EVG150全自动圆片喷雾涂胶系统。该改进后的系统提高了胶的涂覆能力，特别适用于圆片表面复杂的图形结构的涂覆，为微机电系统、先进的圆片级封装、化合物半导体     

背面点接触高效太阳电池的背电场与串联电阻

背面点接触结构提高了硅太阳电池的转换效率，开启电压Ｖ∝和断路电流密度Ｊ∝均有很大的提高和增加，本文针对背面点接触的电池结构，建立了倒棱台单元的模型，通过对背电场与体串联电阻的分析，提出了体串联电阻的计算方法，给出了背面点接触面积和间距的优化设计条件。     

AZ4620光刻胶的喷雾式涂胶工艺

对于一些MEMS应用,需要在形貌起伏很大的晶圆表面均匀地涂布光刻胶。喷雾式涂胶工艺满足了这些要求。研究了几种稀释的AZ4620光刻胶溶液的雾化喷涂性能,在沈阳芯源微电子设备有限公司KS-M200-1SP喷雾式涂胶机上进行了雾化喷涂试验,分别对裸片及深孔不同尺寸的晶圆进行喷雾式涂胶实验;特别研究了决定喷涂薄膜膜厚和均匀性...     

晶圆减薄过程TTV调整技术研究

晶圆背面减薄是集成电路后封装关键工艺,通过金刚石磨轮的磨削作用,对芯片背面的基体材料-硅材料去除一定的厚度,从而降低芯片厚度,改善芯片的散热效果,有利于后期的封装工艺。主要介绍了在晶圆减薄过程中的关键指标TTV 的影响因素,通过设备自动控制,进行工艺角度调整,能够减小晶圆TTV 值,从而提高晶圆磨削质量。     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

硅片背面软损伤工艺技术研究

硅中的金属离子杂质会明显降低少子寿命,并进一步影响硅器件的性能。因此对硅片背面喷砂工艺进行了系统的研究。通过喷砂工艺,在硅片背面形成软损伤层,使硅片具有了吸杂能力,并从吸杂机理出发,解决了吸杂工艺带来的硅抛光片表面颗粒效应,并对硅抛光片的吸杂效果及表面颗粒度进行了表征,为具有吸杂性能的“开盒即用”硅抛光片的批量化生产提供了有力的技术保证。     

Pseudo epi-cost reduction approach and a paradigm shift in substrate material

Historically, P/P+ epitaxial wafers have been utilized for CMOS products for more than two decades. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen-free active areas, superior oxide quality, and gettering capability compared to bulk nonepi wafers. The epi wafers, however, are costly. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 20%-25%. Pseudo epi or high-temperature hydrogen anneal is expected to save a significant percentage of start material costs over the epi substrate for logic family products where epi wafers have dominated the market.     

用于大批量制造环境的薄晶圆处理——传送和加工技术

在半导体生产商不断推进器件和圆片厚度薄型化的形势下,为满足与新产品和加工工艺有关的生产工艺挑战,必须采用更新的分裂方法。新面世的产品射频识别标签,更完善的IC卡以及集成度更高的存储器件,随着更新的从逻辑到存储器及图像传感器各种产品先进封装技术的来临,需要越来越薄基片。对此提出了一种基于临时键合以及新颖的粘接剂技术的适合于薄圆片传送和处理加工的完全解决方案(设备,材料以及工艺过程)。这种方法与25μm以下厚度圆片以及在原有设备没有变更的现有生产线进行薄圆片产品发展路线图加工工艺相适应。     

The nature of particle generation in vacuum process tools

Particle levels in a variety of VLSI process tools are shown to have relatively constant baselines punctuated by short bursts. That these excursions decay rapidly while the baseline remains constant suggests that a strong feedback mechanism exists to hold particle levels in equilibrium. It is shown that this equilibrium is a function of process and wafer conditions and can be disrupted, for example, by running monitor wafers instead of product wafers. This implies that process monitoring methodologies using monitor wafers must be used with caution. The bursts are shown to have a strong potential yield effect when multiple process steps are considered. This effect is strongest when products are early in their life cycle or relatively sensitive to defects     

GaAs pHEMT-based technology for microwave applications in a volume MMIC production environment on 150-mm wafers

The establishment of a 150-mm (6-in) gallium arsenide (GaAs) facility is described together with the development of very high yielding and cost-effective semiconductor device technologies and a manufacturing capacity of over 40000 wafers/annum. The background to the demand for very high volumes of RF products for this market is discussed, together with the prospects for future growth. The paper describes recent process development by the utilization of a data-driven yield management system to support the delivery of high-quality RF products to customers. Finally, "end of line" DC and RF testing of finished 150-mm GaAs pHEMT foundry wafers is described, enabling scalar measurements of power, noise, and intermodulation products as well as vector measurements of S-parameters and noise parameters at frequencies of up to 40 GHz.     

Defect requirements for advanced 300 mm DRAM substrates

In the background of increasing requirements for advanced 300 mm DRAM substrates, the possibilities of balancing defect requirements versus cost and feasibility are discussed. For DRAMs based on deep trench capacitors, the main focus regarding defects is on voids, so-called crystal originated pits (COPs), which are present in the commonly used vacancy rich silicon crystals. Whereas for the material used for recent DRAM design rules, the typical COP sizes around 150 nm have still been sufficiently small not to deteriorate the yield of the DRAM products, for future design rules a reduction of COPs in the device active area will be required. Since the conversion to 300 mm wafers is purely cost driven, a solution has to be found for making 300 mm low defect wafers cost effective for the usage even on products under a high cost pressure like DRAM.A promising material option is 300 mm high temperature annealed wafers, which are on the one hand able to fulfil the future requirements in terms of performance and offer on the other hand also the potential to become a cost effective substrate by implementation of cost saving opportunities. The task of the wafer users is to critically review the requirements and to identify essential needs in contrast to “nice to have” items. For 300 mm annealed wafers, the requirements regarding COP reduction and slip performance are discussed.     

创新型超薄IC封装技术

圆片薄型化工艺技术的改进,以及对小型化、便携式产品的强烈的市场需求,共同推动了封装技术的创新。文中主要论述了与超薄型集成电路封装技术相关的薄型硅集成电路应用、超薄型圆片的制造、薄型化切割技术、同平面互连技术、倒装片装配及其可靠性问题。     

Client-configurable eight-channel optical add/drop multiplexerusing micromachining technology

A client-configurable optical add/drop multiplexer (OADM) is demonstrated using a micromachined 8×6 matrix switch. The matrix switch can be configured to add/drop any of the eight input channels from/to any of the six add/drop ports. For the switching fabric, the insertion loss is 2~3 dB for the dropped channels and 8~9 dB for the added channels by using the backsides of the micromirror switches. The switching extinction ratio is over 40 dB, the crosstalk between channels is less than -40 dB, and they are equipment-limited in this experiment