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半导体工艺中的光刻是芯片制造中最关键的工艺。DFB半导体激光器的腔体结构与普通半导体激光器的腔体结构不同,需要制作周期光栅,光栅周期为亚微米数量级;鉴于亚微米光栅曝光系统在半导体激光器的应用需求,瑞士一家公司研制了一款专用于亚微米周期光栅的设备Phabler 100M DUV光刻机;本系统采用了非线性晶体的倍频效应和周期性光栅的泰伯效应。这些关键技术用较低的成本实现了极高的分辨率,可以制作周期性光栅并达到100 nm的线条分辨率;掩模版和晶片的不平行将造成光刻线条的不均匀,应用CCD探测器和计算机相结合的办法是做平行度的关键调试。 相似文献
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<正>亚微米微位移机构是现代精密机械与精密仪器的共同基础。近年来随着科学技术的发展,尤其是微电子技术的飞跃进步,将精密机械与精密仪器的精度提高了一个数量级,即由微米级的精度提高到亚微米级,因此作为精度补偿及微调机构的亚微米微位移技术,得到了迅速的发展和广泛地应用。目前亚微米微位移技术日趋成熟,实现亚微米微位移的方法很多,本文着重讨论电磁驱动原理,位移机构设计中的问题以及利用该原理设计研制的亚微米微位移机构的实验结果。 电磁驱动原理 相似文献
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正在向一微米和0.5微米级电路发展的半导体工业总是以相应的制造工艺作为其技术保障的。本文所研究的是作为亚微米器件制作方法的光学光刻法,电子束微光刻法,远紫外和X射线微光刻法的特性。 相似文献
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从美日之争看微纳米半导体技术的研究与发展 总被引:1,自引:0,他引:1
美国与日本在微米半导体和纳米半导体领域的竞争由来已久。1986~1992年日本在微米半导体方面领先于美国,尤其在DRAM领域,NEC、东芝和日立成为世界最强的前三名半导体公司,日本成为世界头号半导体大国。1993年至今美国在亚微米、深亚微米半导体的竞争中战胜了日本,尤其在微处理器、微控制器、标准逻辑器件、闪存、PLD和模拟器件等领域,英特尔成为世界最大的半导体公司,美国再次登上世界半导体市场的头把交椅。近10年,日本在纳米半导体领域向美国挑战,日本在纳米技术的许多方面领先于美国,两国的竞争正处于白热化。 相似文献
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日本超LS1技术研究组合共同研究所的直到0.25微米的线条与间隔图形,被选为划时代的剥离技术。为更进一步将此技术用于布线,所以也同时研制了金属化工艺,这些都在十二月举行的电子通信学会半导体与晶体管研究会上发表了。 剥离技术作为高精度加工方法是超LS1等的亚微米器件所不可缺少的技术。用以往的加工方法,由于部分剥离不成功 相似文献
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不久前,Aviza公司与中国最大的半导体设备制造商北京七星华创电子公司签约,向中国引进生产Aviza科技公司设备的技术。该协议规定,七星华创将制造专门针对中国半导体制造商需要的Aviza科技公司亚微米级热加工和沉积系统。 相似文献
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本文地亚微米工艺设计规则进行探讨,旨在促进设计公司与Fab厂家之间信息反馈,共同努力并顺利进入亚微米和深亚微米领域。 相似文献
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本文叙述了当前世界上亚微米、深亚微米技术的发展趋势,分析了我国亚微米技术的现状,最后介绍了机械电子工业部第十三研究所在亚微米技术方面的进展及其在半导体器件与集成电路制造中的成功应用。 相似文献
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Parikh P.A. Jiang W.N. Chavarkar P.M. Kiziloglu K. Keller B. DenBaars S.P. Mishra U.K. 《Electron Device Letters, IEEE》1996,17(7):375-377
The super self-aligned submicron single-metal FET (SASSFET), a FET-based integrated circuit technology suitable for fabrication of high-speed GaAs and InP circuits, is demonstrated. With nonalloyed source and drain contacts realized by MOCVD regrowth, the SASSFET is a uniform, dense, selfaligned, single-metal technology that achieves submicron dimensions with optical lithography. A 0.4 μm gate length junction HFET fabricated with the SASSFET technology has a transconductance of 380 mS/mm and a good high-frequency performance with fτ of 45 GHz and fmax of 80 GHz 相似文献
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随着深亚微米集成电路技术的发展,集成电路的规模越来越大,工作频率越来越高,并正朝着系统集成的方向发展,因而在模拟速度,模拟精度和可模拟的电路规模等各个方面对电路仿真技术提出了新的要求。近年来,各种新的电路仿真方法和仿真系统用相继脱颖百出,并将取代那些传统的,已经无法适应深亚微米技术发展的电路仿真器。 相似文献
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A bus energy model for deep submicron technology 总被引:2,自引:0,他引:2
Sotiriadis P.P. Chandrakasan A.P. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2002,10(3):341-350
We present a comprehensive mathematical analysis of the energy dissipation in deep submicron technology buses. The energy estimation is based on an elaborate bus model that includes distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a closed form. The notion of the transition activity of an individual line is generalized to that of the transition activity matrix of the bus. The transition activity matrix is used for statistical estimation of the power dissipation in deep submicron technology buses. 相似文献
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The effect of scaling down the channel width on the threshold voltage of deep submicron MOSFETs with LOCOS isolation has been investigated. Previous results, obtained from 1 μm technology and above, show an increase in threshold voltage as the width is reduced. However, in deep submicron technology, oxide thickness is scaled-down and channel doping is increased to avoid punchthrough and maintain a sufficiently high threshold voltage. This results in a threshold voltage reduction as channel width is scaled-down—the so called Inverse-Narrow-Width-Effect (INWE). The trend is explained through dopant redistribution and is verified by both experiment and process simulation. Lastly, a new narrow width threshold voltage model is proposed to account for the dopant redistribution effect. 相似文献
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One of the main problems in the topological transformation of submicron VLSIs for the double lithographic mask technology is the decomposition of the initial topological layer into two new ones. Transformation algorithms of the VLSI topology for the double lithographic mask technology, which are oriented towards the application of high-performance computing systems, as well as the results of experimental investigations, which are performed using the developed software, are discussed. The advantages and disadvantages of the suggested approaches are discussed. 相似文献
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The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 μm and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity 相似文献