面向RTOS的嵌入式软件模拟器构造与实现方法

提出一种快速嵌入式软件验证工具——RTOS软件模拟器。在RTOS软件模拟器验证方法中,利用RTOS模块化、层次化设计特点,快速实现嵌入式软件在不同目标机器间的代码移植,通过扩展RTOS API功能,建立硬件模拟驱动,实现软件模拟器和硬件模拟器通信连接和协同模拟同步控制。RTOS软件模拟器克服ISS速度低的缺点,从更高层次验证嵌入式软件功能。     

大型船舶操纵模拟器的硬件设计与应用

设计了大型船舶操纵模拟器操作台上常用的硬件设备,并对该硬件系统的总体架构以及设备的软硬件设计进行了详细介绍。该模拟器遵循STCW公约马尼拉修正案,满足中国海事局有关规定的性能标准,具有广泛的市场前景,并已投入到国内多家航海院校的教学培训中,取得了良好的效果。     

基于ISS和硬件模拟器的协同模拟关键技术研究

提出一种在嵌入式系统软硬件协调设计中对系统功能进行验证的软硬件协同模拟方法．该方法使用指令集模拟器(ISS)和事件驱动硬件模拟器分别完成软硬件的模拟,并采用C 语言构造处理器的总线功能模型,实现软硬件模拟器的信息交互．重点讨论指令集模拟器、总线功能模型以及硬件模拟器协同模拟接口的设计与实现方法,同时还给出了软硬件模拟器之间的同步算法．     

面向协同产品商务的敏捷设计支持系统的研究

叙述了协同产品商务(CPC)出现的背景，对CPC定义作了进一步解释，阐明CPC所具有的三个特点及其内涵．将CPC引入产品协同设计，提出产品敏捷设计的概念．构造了面向CPC的产品敏捷设计支持系统，说明了该系统的功能及体系结构，以递纸机构设计为例验证了系统应用．     

浅析教学模拟器的设计

当前的教学实践课程越来越广泛地引入教学模拟器为教学手段。一部好的模拟器不仅可以解决教学实践中实装设备配置不齐及价格昂贵等问题,更能提高实践课程的教学效果。本文对教学模拟器设计的各个阶段进行了探讨,对如何设计出一部可靠的教学模拟器提出了一些可行的方法。     

某型鱼雷模拟器的设计与实现

分析了某型鱼雷模拟器的基本功能,比较了嵌入式和"微机+插板"设计方案的特点,并给出了基于后者的总体结构设计;详细讨论了鱼雷模拟器中的ITA计数和预置参数接收两个主要功能的硬件电路设计和软件开发,确保鱼雷模拟器基本功能的实现;为提高鱼雷模拟器的可靠性和功能,给出了各自对应自检功能的硬件电路设计和软件开发和故障模拟的软件实现。     

嵌入式系统软件模拟器设计

利用软/硬件协同设计的方法,将嵌入式系统设计采用软件模拟系统环境来开发,通过对CPU行为、内存、中断控制器和操作系统等模块的设计,把硬件系统设计和软件系统仿真相结合。是目前嵌入式系统设计的全新的方法。通过实例对软件模拟器进行验证,表明了这种方法的可行性和可靠性,为嵌入式系统的开发提供软件系统仿真的经验。     

让设计敏捷起来

“敏捷制造”的概念众所周知。但是“敏捷设计”的概念似乎并没有被企业用户所熟知。     

Verifying the summit bus converter protocols with symbolic model checking

We report on our investigation of a new verification tool, the Symbolic Model Verifier (SMV), created at Carnegie Mellon University. We have successfully, employed this tool to detect deadlock in an industrial design, namely, Hewlett-Packard's Summit bus converter chips. In addition to locating a known deadlock in the original chip design and checking its solution, we successfully detected other previously unknown defects in the design. In our experiments, we were able to verify properties on finite-state models of the circuit with 150 to 200 state variables in a matter of minutes.     

面向硬件教学的模拟机设计与实现

随着计算机技术的飞速发展,传统的计算机硬件教学用计算机已经不能适应当前的要求.对面向硬件教学的模拟机的系统架构进行了研究,归纳总结了模拟机的设计步骤和仿真实现方法.从CPU指令系统构架的确定开始,进行指令集,数据通路和控制通路的设计,最后通过面向对象技术实现模拟机系统.该系统不仅为计算机硬件教学提供了一个灵活开放的平台,而且对于开展CPU技术和计算机体系结构的研究也具有重要价值.     

Formal hardware verification methods: A survey

Growing advances in VLSI technology have led to an increased level of complexity in current hardware systems. Late detection of design errors typically results in higher costs due to the associated time delay as well as loss of production. Thus it is important that hardware designs be free of errors. Formal verification has become an increasingly important technique towards establishing the correctness of hardware designs. In this article we survey the research that has been done in this area, with an emphasis on more recent trends. We present a classification framework for the various methods, based on the forms of the specification, the implementation, and the proff method. This framework enables us to better highlight the relationships and interactions between seemingly different approaches.     

Fuzzy logic based smart traffic light simulator design and hardware implementation

The objective of this study is to develop fuzzy logic based traffic junction light simulator system for design and smart traffic junction light controller purposes and also to observe its performance. Traffic junction simulator hardware is developed to overcome difficulties of working in a real environment and to easily test the performance of the controller. By using the traffic light simulator developed in this study, results of constant duration (conventional) traffic light controller and fuzzy logic based traffic light controller are compared where the vehicle inputs are supplied by the simulator. Statistical experimental results obtained from the implemented simulator show that the fuzzy logic traffic light controller dramatically reduced the waiting time at red lights since the controller adapts itself according to traffic density. It is obvious that the intelligent light controller is going to provide important advantages in terms of economics and environment.     

An environment for formal verification based on symbolic computations

We present an environment for formally verifying hardware, based on symbolic computations. This includes a new concurrency model, called the combinational/sequential or C/S concurrency model which has close ties to hardware. We allow fairness constraints and describe methods for specifying them and for formally verifying in their presence. Properties are specified by either CTL formulae or edge-Rabin automata. We give algorithms, in the presence of fairness constraints, for model checking CTL or for checking that the language of our system is contained in the language of a property automation. Finally, techniques are given for hierarchical verification and for detecting errors quickly (early failure detection).     

一种电子负载模拟器方案设计

为了更加便捷的开展航天器各项大型试验和测试工作,研制了一种电子负载模拟器。电子负载模拟器能够模拟航天器电气系统的压力传感器、电磁阀、自锁阀、温度传感器、火工品等负载的电压和电流信号特性,并完成负载电压的采集和负载通电时间的统计,同时将所有功能模块集成到一个标准机箱中,所有电气信号接口通过若干接插件汇总对外进行连接,各功能模块通过上位机软件进行通信和控制。电子负载模拟器参与了某型号航天器的模飞测试工作,测试数据准确无误且性能稳定,既验证了上游驱动电路的电气匹配特性,又节省了梳理负载电缆和插拔接插件的繁琐性,同时也降低了人员频繁插拔接插件的出错概率。     

面向众核系统的层次化栅栏同步机制

同步操作在保证多核处理器线程的数据一致性和正确性等方面起着重要作用。随着处理器内核数量的不断增加,同步操作的开销也越来越大。栅栏同步是并行应用中多核同步的重要方法之一。软件同步方法通常需要数千个周期才能完成多个内核之间的同步,这种高延迟和串行化同步会导致多核程序性能的显著下降。相比于软件栅栏同步方法,硬件栅栏能够实现较低的同步延迟,然而传统集中式硬件栅栏的可扩展性有限,难以适应众核处理器系统的同步需求。面向众核处理器提出了一种层次化硬件栅栏机制——HSync,它由本地栅栏单元和全局栅栏单元组成,二者协调配合,以实现低硬件开销的快速同步。实验结果表明,与传统的集中式硬件栅栏相比,层次化硬件栅栏机制将众核处理器系统性能提高了1.13倍,同时网络流量减少了74%。     

JPEG图像硬件解码低功耗设计

分析了JPEG标准的压缩/解压缩算法,以VLSI方式实现了基于JPEG标准的解码流程,在关键模块--Huffman解码、IDCT上进行了算法级、结构级和电路级等层次的综合考虑,使其有更好的功耗代价,使其能够在图像传感器上得到应用.通过测试平台对其VLSI进行了RTL级和门级的仿真.结果表明,功能符合需求.