A multiconductance silicon neuron with biologically matched dynamics

We have designed, fabricated, and tested an analog integrated-circuit architecture to implement the conductance-based dynamics that model the electrical activity of neurons. The dynamics of this architecture are in accordance with the Hodgkin-Huxley formalism, a widely exploited, biophysically plausible model of the dynamics of living neurons. Furthermore the architecture is modular and compact in size so that we can implement networks of silicon neurons, each of desired complexity, on a single integrated circuit. We present in this paper a six-conductance silicon-neuron implementation, and characterize it in relation to the Hodgkin-Huxley formalism. This silicon neuron incorporates both fast and slow ionic conductances, which are required to model complex oscillatory behaviors (spiking, bursting, subthreshold oscillations).     

Analog circuits for modeling biological neural networks: design andapplications

Computational neuroscience is emerging as a new approach in biological neural networks studies. In an attempt to contribute to this field, we present here a modeling work based on the implementation of biological neurons using specific analog integrated circuits. We first describe the mathematical basis of such models, then present analog emulations of different neurons. Each model is compared to its biological real counterpart as well as its numerical computation. Finally, we demonstrate the possible use of these analog models to interact dynamically with real cells through artificial synapses within hybrid networks. This method is currently used to explore neural networks dynamics.     

Parametric least squares approximation using gamma bases

We study the problem of linear approximation of a signal using the parametric gamma bases in L² space. These bases have a time scale parameter, which has the effect of modifying the relative angle between the signal and the projection space, thereby yielding an extra degree of freedom in the approximation. Gamma bases have a simple analog implementation that is a cascade of identical lowpass filters. We derive the normal equation for the optimum value of the time scale parameter and decouple it from that of the basis weights. Using statistical signal processing tools, we further develop a numerical method for estimating the optimum time scale     

Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive relaxation (SR) method for solving the fixed-point problem. We observe that SR with the optimal relaxation factor can considerably improve the error-rate performance of iterative decoding for short low-density parity-check (LDPC) codes, compared with SS. Our simulation results for the application of SR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations, and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to an infinite maximum number of iterations and infinitesimal relaxation factor, represents the steady-state performance of analog iterative decoding. This means that under ideal circumstances, continuous-time (asynchronous) analog decoders can outperform their discrete-time (synchronous) digital counterparts by a large margin. Our results also indicate that with the assumption of a truncated Gaussian distribution for the random delays among computational modules, the error-rate performance of the analog decoder, particularly in steady state, is rather independent of the variance of the distribution. The proposed simple model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits.     

On the architecture and performance of a hybrid image rejectionreceiver

This paper describes a hybrid image rejection receiver. The hybrid image rejection receiver contains a modified Hartley (1928) image rejection mixer and a digital image rejection processor. The modified Hartley image rejection mixer performs similarly to an original Hartley image rejection receiver but provides two digital outputs. In one output it enhances the desired signal and in the other output it enhances the image signal. The digital image rejection processor first measures the mismatching effect in the analog devices and then suppresses the image signal by compensating for the mismatching effect. We also propose a simplified implementation method for the hybrid image rejection receiver to reduce its computation complexity. Computer simulation was used to evaluate the performance of this simplified implementation method to include the quantization effect introduced by the A/D converters. Simulation results show that the proposed hybrid image rejection receiver achieves much better performance than the original Hartley image rejection receiver. This architecture greatly relaxes the matching requirements of the analog devices and has a low complexity for an IC implementation     

智能化多媒体教室中语音传输系统的设计与实现

语音信号在智能化多媒体教室中起着非常重要的作用.本文从语音模拟信号和数字信号的传输两个方面,分别阐述了语音传输系统的构成和实现：模拟信号在教室内传输、数字信号在网络中传输.不同的传输方式,使用的设备和技术手段不同,最终都以获得优质语音信号,促使多媒体教室正常运行,为教育教学服务为目的.     

自适应Sigma-Delta A/D转换器的设计

对于传统的Sigma-Delta A/D转换器(ADC),其信噪比(SNR)将随着输入信号强度的减小而降低.因此,本文根据自适应理论提出一种自适应ADC的解决方案及相应的电路实现.在充分考虑了在电路实现中误差的存在,给出了误差自校正电路.仿真结果表明,这种自适应ADC的SNR几乎与输入信号的强度无关.     

Preface to the Special Topic on Devices and Circuits for Wearable and IoT Systems

The concept of Internet of Things (IoT) was first proposed by MIT Prof.Kevin Ash-ton in 1999.The implementation of IoT was mainly through RFID in its early time.With advanced technology and manufacture,diverse implementation forms ofIoT are becoming possible.Wearable devices,as an essential branch of IoT,will have broad application prospects in health monitoring and intelligent healthcare.     

On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints

In the context of biosensor as much as Built-In-Self Test (BIST), on-chip sine-wave signal generation is a recurring research topic. Considering the implementation constraints, it implies a trade-off between the amount of resources and the signal quality. An attractive solution consists in combining several digital signals to build this analog sine-wave. The objective of this paper is to give an analytic study of various potential digital-based solutions. Thanks to this study, we prove that the technique consisting in setting the phase shifts and various amplitude values of the square-wave signals is the most efficient approach. This study allows the selection of the optimal square-wave signal parameters to cancel low-order harmonics of the generated signal. We proposed a solution for specification-oriented definition of the architecture.     

基于细胞神经网络的从阴影恢复形状的新方法

细胞神经网络(CNN)是一种实时处理信号的大规模非线性模拟电路,它的连续时间特点以及局部互连特点使其可以进行并行计算,并且非常适用于超大规模集成电路(VLSI)的实现.本文针对从阴影恢复形状(SFS)问题,提出了一种基于硬件退火CNN的能量函数优化方法,并对该方法进行了详细分析,给出了实例的仿真结果,验证了该方法的有效性.该方法为并行处理算法,具有运算量小、易于大规模VLSI集成实现,且能够克服局部极小等优点,可以使SFS问题得到实时的处理.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speedwireless applications [LANs]

A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2-μm double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64-chip correlators recover the 2-Mb/s data stream from the doubly modulated [pseudorandom noise (PN) and Walsh] quadrature input signal. An on-chip 10-b pipelined ADC sampling at 8 MS/s follows the analog correlation to permit digital implementation of the acquisition and tracking algorithms     

Compressed Sensing of Analog Signals in Shift-Invariant Spaces

A traditional assumption underlying most data converters is that the signal should be sampled at a rate exceeding twice the highest frequency. This statement is based on a worst-case scenario in which the signal occupies the entire available bandwidth. In practice, many signals are sparse so that only part of the bandwidth is used. In this paper, we develop methods for low-rate sampling of continuous-time sparse signals in shift-invariant (SI) spaces, generated by m kernels with period T . We model sparsity by treating the case in which only k out of the m generators are active, however, we do not know which k are chosen. We show how to sample such signals at a rate much lower than m/T, which is the minimal sampling rate without exploiting sparsity. Our approach combines ideas from analog sampling in a subspace with a recently developed block diagram that converts an infinite set of sparse equations to a finite counterpart. Using these two components we formulate our problem within the framework of finite compressed sensing (CS) and then rely on algorithms developed in that context. The distinguishing feature of our results is that in contrast to standard CS, which treats finite-length vectors, we consider sampling of analog signals for which no underlying finite-dimensional model exists. The proposed framework allows to extend much of the recent literature on CS to the analog domain.     

Non-idealities Compensation in Full-Digital Receivers with Application to Ultra-Wide Band

Nowadays many transceivers adhere to full-digital design principles, with the basic operations performed in the analog domain (filtering, down-conversion) and the whole remaining processing postponed to the digital domain (including matched filtering and synchronization). Though the operations in the analog front-end are ideally reversible, hence no signal degradation should occur before the analog-to-digital conversion (thus preserving the information integrity), however the intrinsic non-idealities in the circuitry may introduce a certain level of distortion. In this paper we provide a simple and flexible approach for the compensation of these effects. We derive useful formulas for obtaining a digital compensation filter by means of a direct transformation of the analog system coefficients. This allows to easily perform the compensation in the digital domain via fast Fourier transform. To illustrate the procedure, the case-study of a ultra-wide band receiver is addressed. Numerical results show that an improvement of more than 1 dB can be obtained at bit-error rate of interest for the applications. Sample code is also provided for an easy implementation.     

A new interpolation technique for time interleaved \Upsigma\Updelta A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area and the order of the anti-alias filter but also improves A/D converter performance. The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65?nm CMOS process.     

Implementing the Lorenz oscillator with translinear elements

Nonlinear processing is often more suitable than the traditional linear approach is for analyzing biological signals. Unfortunately, digital nonlinear operations are computationaly expensive. In contrast, a large variety of nonlinear operations can efficiently be implemented in analog electronics, operating at real-time speeds. The low level of accuracy generally associated with analog processing is not a concern in this scenario, as biological signals themselves typically have low signal-to-noise ratios. One challenge of analog processing is in its apparently-ad hoc design, and the fact that there is very little wide-spread knowledge of systematically implementing analog electronics to perform arbitrary nonlinear computations. Another issue is the integrity of the analog components; the analog properties of electronic devices are prone to a large amount of mismatch. In this paper, we examine multiple-input translinear element (MITE) networks, a class of analog circuits that addresses the two concerns of a structured synthesis procedure and component mismatch. We test the ability of these MITE networks for accurately realizing linear and nonlinear systems with prescribed dynamics by attempting to implement the Lorenz equations. We will present the theoretical procedure, address practical implementation issues, and then show experimental results from a version of the circuit fabricated in a 0.5 μm CMOS technology through MOSIS.     

Compression at the Physical Interface [The A-to-I and MONTAGE programs]

This article focuses on recent progress in physical compressive sampling under the Defense Advanced Research Agency's Analog-to-Information (A-to-I) and Multiple Optical Non-Redundant Aperture Generalized Sensors (MONTAGE) programs. A-to-I and MONTAGE focus on aggressive forms of generalized sampling under which measurements consist of transformations, projections, or encodings of the signal onto discrete digital data. The central system design challenge is to select features, sampling strategies and hardware that enable high fidelity signal estimation from these features. The A-to-I and MONTAGE projects differ in application and implementation A-to-I seeks to revolutionize very high temporal bandwidth analog to digital signal conversion whereas MONTAGE seeks to revolutionize very high spatial bandwidth analog to digital signal conversion.     

Convergence Speed and Throughput of Analog Decoders

This letter is concerned with the implementation of iterative decoding algorithms in analog integrated circuits. We study the convergence speed and the throughput of analog decoders for low-density parity-check codes, and show that they depend on the code, the decoding algorithm, the signal-to-noise ratio, and the average time constant of the analog circuit interconnections. However, they are not a function of the variance of the time constants. The analysis presented here can be used for selecting suitable codes and decoding algorithms for analog decoding. Furthermore, it can be used to estimate the throughput of an analog decoder, if the average time constant of the analog circuit is known