Three-dimensional representation and quantification of endosomes in the rat kidney proximal tubule cell.

The organization of the endosomal compartment in the rat kidney proximal tubule cell was studied by computer-aided three-dimensional reconstruction based on tracing of serial thin sections. Besides the well-documented endocytic elements such as small vesicles, tubules and large vacuoles, the endosomal compartment contained a prominent structural complex consisting of a central vacuolar element (with diameters up to 2000 nm) and associated systems of radiating tubular profiles. The large endosomes examined had from two to twenty-four tubules as straight or bending extensions directed randomly from the central vacuole. The tubules were 70-90 nm in diameter and varied with the length up to 1500 nm. Quantitative evaluation from examples of the large endosomes with more than ten tubular extensions, showed that 25-40% of the membrane resided in the tubular portion in contrast to 5-10% of the volume. These results indicate the high efficiency of the role of the endosomal tubules as a mediator of the membrane recycling, because the tubules simultaneously allow retention of most of the content in the central vacuole during the recycling process.     

Three-dimensional displays

Three-dimensional display techniques can be classified as binocular and autostereoscopic types, still and animated types, nontransmitted and transmitted types, and nonholographic and holographic types. This paper deals mainly with autostereoscopic still nontransmitted techniques. Holographic and nonholographic tecniques are described on about equal footing. For the sake of brevity, emphasis is placed upon those techniques that appeared in the past several years. However, some old techniques of historical and/or practical importance are also mentioned because rather few textbooks are available in this field. In the final part, state of the art of three-dimensional display for animated and transmitted images (three-dimensional television) is described. Speculations on the direction of the development are presented.     

小鼠精原细胞在生精小管内迁移的研究

小鼠睾丸发生的过程中 ,从原始生殖细胞到各级生精细胞在时间、空间上的迁移 ,最终到达生殖腺嵴和睾丸索 ,这是睾丸发生、发育过程中的一个相当重要的阶段 [1]。近几年来 ,由于离体研究的运用 ,揭示了睾丸索出现以前原始生殖细胞的运动过程及其存活、增殖的条件[2 - 3] 。睾丸索出现以后 ,对其内部精原细胞迁移及其与精原细胞凋亡、生精小管空腔出现的关系研究尚不多见。鉴于此 ,本研究采用昆明种小鼠 ,研究了生精小管内精原细胞迁移变化的规律 ,希望能为男性生育的临床研究提供理论依据及动物实验的资料。材料和方法选用健康昆明种雄性小鼠…     

The time-triggered architecture

The time-triggered architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time application is decomposed into nearly autonomous clusters and nodes, and a fault-tolerant global time base of known precision is generated at every node. In the TTA, this global time is used to precisely specify the interfaces among the nodes, to simplify the communication and agreement protocols, to perform prompt error detection, and to guarantee the timeliness of real-time applications. The TTA supports a two-phased design methodology, architecture design, and component design. During the architecture design phase, the interactions among the distributed components and the interfaces of the components are fully specified in the value domain and in the temporal domain. In the succeeding component implementation phase, the components are built, taking these interface specifications as constraints. This two-phased design methodology is a prerequisite for the composability of applications implemented in the TTA and for the reuse of prevalidated components within the TTA. This paper presents the architecture model of the TTA, explains the design rationale, discusses the time-triggered communication protocols TTP/C and TTP/A, and illustrates how transparent fault tolerance can be implemented in the TTA.     

Scalar supercomputer architecture

High-performance scalar architectures that have the capability to issue multiple instructions per clock period are considered. The essential characteristics and the principal architectural tradeoffs in scientific array processors, very-long-instruction-word (VLIW) machines, the polycyclic architecture and decoupled computers are examined. Array processors rely solely on static code scheduling done manually or by the compiler. The scheduling task is quite complex, and the resulting code may not be very efficient. In a VLIW, sophisticated compiler technology provides software solutions for functions traditionally done in hardware. The polycyclic architecture is similar to array processors in its structure but provides architectural support to the instruction scheduling task. In decoupled architectures the hardware changes the order of instruction execution at run time. This dynamic code scheduling capability does not come at the expense of additional control complexity     

电子政务安全体系

本文从加密算法、安全协议、网络安全、操作系统安全和应用安全等五个方面,介绍了电子政务安全体系。     

Flash memory architecture

Flash memories entered the nonvolatile memory scenario only a few years ago, and now these kind of memories are battling to substitute either EEPROM or EPROM. In fact, their peculiarities are becoming quite interesting in present day applications.In system updating, low power consumption, embedded algorithm for program and erase, high density, low cost packages are some of the items which are making the Flash grow in the nonvolatile memory market share.Some words must be spent in explaining what the market is asking of Flash, which are the main applications for these memories, and how their architecture is arranged.The Flash memory cell behaviour will be described, then the fundamental operations (read, program and erase) are explained and some words are used to introduce the redundancy and device testability concept.     

Antenna array architecture

An abbreviated view of the topics included in modern array architecture is presented. The broad subject of architecture includes all the electromagnetic, thermal and mechanical aspects that need to be addressed by the array design team. The emphasis is on the interaction between the selection of an array aperture organization, corporate feeds, devices and elements, and a discussion of EHF monolithic array architecture is included as an example     

Open architecture controllers

Open architectures for desktop computing revolutionized the office. The author looks at how computer numerical controllers for factory equipment may be next     

Flash ADC architecture

A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2/sup (N-2)/+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86/spl times/10/sup -15/. /spl Delta/f(V/sup 2/) at this frequency.     

The PacketCable architecture

PacketCable^TM defines a multimedia system architecture that overlays a high-speed cable modem access network, with the goal of enabling a wide variety of Internet protocol-based multimedia services, such as voice over IP, unified messaging, PBX extension, videoconferencing, and online gaming. Currently, the architecture provides a complete solution for delivering VoIP services. We present the core capabilities necessary to implement such services in a scalable fashion. Next, we describe the major functional components that comprise the PacketCable architecture and illustrate how they work together to form an integrated IP multimedia-enabled system architecture, which is presently focused on voice over IP. Finally, we present some possible next steps in the evolution of PacketCable     

Linear voltage-controlled-impedance architecture

A circuit is presented for the simulation of electronically tunable impedance. It employs two operational amplifiers, an MOS resistive circuit (MRC) and passive components. It enables the wide range linear tuning of impedance values through the voltage control of the MRC and is therefore well suited for the design of programmable filters and oscillators     

ISDN protocol architecture

IT IS NOW widely recognized that the Integrated Services Digital Network (ISDN) concept is providing a useful framework for the development of future telecommunications networks and services. An ISDN can be regarded as a generalpurpose digital network capable of supporting (or integrating) a wide range of services (voice and non-voice) using a small set of standard multipurpose user-network interfaces. Relevant CCITT Recommendations (or standards) on ISDN interfaces were expected to be available in 1984, the final year of the current study period. This paper reviews CCITT progress on the architectural studies of protocols associated with ISDN's, in particular, the ISDN Protocol Reference Model being developed by Study Group XVIII. This Model, based on the concepts and principles of the ISO/CCITT Open Systems Interconnection (OSI) Reference Model, aims at providing a unified framework for modeling ISDN multiservice communications and capabilities. The new Model is applied to several possible ISDN communications configurations, enabling a number of technical issues to be easily identified.     

基于CAD三维技术的室分系统三维化设计构想

传统的室分系统是基于CAD的2D技术设计的,但是现在的网络结构越来越复杂,针对传统的室分系统做前期分析非常困难且难以检验。CAD的三维技术能够更加具体的显示出建筑的构造,基于CAD三维技术设计的室分系统,更便于对室分系统的前期的分析。     

Three-dimensional CMOS integration

The advantages of CMOS technology are examined, and problems of and approaches to 3-D integration are discussed. Particular attention is given to silicon-on-insulator (SOI) technology and the use of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of monocrystalline silicon. The fabrication of 3-D CMOS devices using these techniques is described     

Three-dimensional Internet developments

This paper describes the application of Internet-based three-dimensional (3-D) user interfaces, comparing them with more traditional two-dimensional (2-D) interfaces. The modelling of 3-D worlds in the Virtual Reality Modelling Language (VRML) is described, together with an overview of VRML and its likely future direction. Multi-user shared environments, which enable Internet users to meet and communicate with each other in cyberspace via avatars (3-D representations of users), are then introduced. A shared information garden is described which allows people to meet and share information in a dynamic, information-rich, virtual environment.     

Three-dimensional IC trends

VLSI will be reaching to the limit of minimization in the 1990s, and after that, further increase of packing density or functions might depend on the vertical integration technology. Three-dimensional (3-D) integration is expected to provide several advantages, such as 1) parallel processing, 2) high-speed operation, 3) high packing density, and 4) multifunctional operation. Basic technologies of 3-D IC are to fabricate SOI layers and to stack them monolithically. Crystallinity of the recrystallized layer in SOI has increasingly become better, and very recently crystalaxis controlled, defect-free single-crystal area has been obtained in chip size level by laser recystallization technology. Some basic functional medels showing the concept or image of a future 3-D IC were fabricated in two or three stacked active layers. Some other proposals of subsystems in the application of 3-D structure, and the technical issues for realizing practical 3-D IC, i.e., the technology for fabricating high-quality SOI crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, will also be discussed in this paper.