In0.52Al0.48As/InxGa1‐xAs(X=0.53, 0.6) Lattice‐matched and pseudomorphic HEMTS on INP substrates

Abstract

In_0.52Al_0.48As/In _x Ga_1‐x As(x=0.53 lattice‐matched, and x=0.6 pseudomorphic) high electron mobility transistor (HEMT) structures are grown by a Riber‐32P MBE system on (100) InP:Fe substrates. Devices with the gate‐length of 0.8μm show excellent channel pinch‐off characteristics from the I_ds‐V_ds curves. The saturation current density biased at V_gs =0.5V is 480 mA/mm for HEMTs(x=0.53) and 550 mA/ mm for pseudomorphic‐(PHEMTs, x=0.6). A peak extrinsic DC transconductance (g_m ) increases from 342 mS/mm to 395 mS/mm as the In composition increases from 53% to 60% for In_0.52Al_0–48As/ In _x Ga_1‐x As HEMTs. Microwave characteristics demonstrate that a current gain cutoff frequency (f_T ) also increases from 22 GHz to 25 GHz and a maximum oscillation frequency (f_max ) increases from 60 GHz to 83 GHz, at 300K. This demonstrates that with the increase of In content in In _x Ga_1‐x As channels, device performance is dramatically enhanced, which can be used for microwave circuit applications.     

Study on pH at the point of zero charge of TiO2 pH ion-sensitive field effect transistor made by the sputtering method

In this article, the current-voltage curve of an ion-sensitive field effect transistor (ISFET) is used to find the pH_pzc (pH at the point of zero charge) of a pH-ISFET device. The pH_pzc is an important parameter of a pH-ISFET device that is used directly to obtain the relationship between the equilibrium constants, K_a and K_b, and pH sensitivity. In this study, titanium dioxide (TiO₂) acted as the sensitive membrane of a pH-ISFET, and was deposited by the sputtering method with a thickness of about 250 Å. A Keithley 236 Semiconductor Parameter Analyzer was used to measure the drain-source current (I_DS) versus the gate voltage (V_G) curve at room temperature. Furthermore, this was used to determine the sensitivity of the TiO₂ pH-ISFET, and then this information has substituted into the theoretical metal oxide semiconductor field effect transistor (MOSFET) model to determine the ISFET threshold voltage. Thus, the surface potentials of the TiO₂ pH-ISFET for different pH values were obtained. Furthermore, it is well known that when the pH is equal to the pH_pzc the surface potential must be zero and accordingly, we attained a pH_pzc of 6.2 for the TiO₂ pH-ISFET.     

Carrier transport mechanisms and photovoltaic characteristics of p-H2Pc/n-Si heterojunctions

Heterojunction cells of p-H₂Pc/n-Si were fabricated by vacuum deposition of p-H₂Pc thin films onto n-Si single crystals. Measurements of the current-voltage (I-V) and the capacitance—voltage (C-V) characteristics have been evaluated to identify the mechanisms of barrier formation and, consequently, current flow. The forward current involves tunneling and could be explained by a multi-step tunneling recombination model due to a high density of interface defects. The C-V characteristics indicate an abrupt heterojunction model. The devices exhibit strong photovoltaic characteristics with an open-circuit voltage of 0.34 V, a short-circuit current density of 17.5 mA/cm² and a power conversion efficiency of 1.5%. These parameters have been estimated at room temperature and under constant illumination of 150 mW/cm².     

SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec^?1 at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS₂ van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS₂ vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS₂ as the channel, the SnSe/MoS₂ vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltage V_P of ?0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec^?1 and high ON/OFF ratio over 10⁶, demonstrating excellent electronic performance especially in the subthreshold regime.     

Effects of LiF/Al back electrode on the amorphous/crystalline silicon heterojunction solar cells

To improve the quantum efficiency (QE) and hence the efficiency of the amorphous/crystalline silicon heterojunction solar cell, we have employed a LiF dielectric layer on the rear side. The high dipole moment of the LiF reduces the aluminum electrode's work–function and then lowers the energy barrier at back contact. This lower energy barrier height helps to enhance both the operating voltage and the QE at longer wavelength region, in turn improves the open-circuit voltage (V_oc), short-circuit current density (J_sc), and then overall cell efficiency. With optimized LiF layer thickness of 20 nm, 1 cm² heterojunction with intrinsic thin layer (HIT) solar cells were produced with industry-compatible process, yielding V_oc of 690 mV, J_sc of 33.62 mA/cm², and cell efficiencies of 17.13%. Therefore LiF/Al electrode on rear side is proposed as an alternate back electrode for high efficiency HIT solar cells.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

The Role of the Gate Geometry for Cryogenic HEMTs: Towards an Input Voltage Noise Below 0.5~\mathrm{nV}/\sqrt{\mathrm{Hz}} at 1 kHz and 4.2 K

Specific HEMTs (High Electron Mobility Transistors) with different gate geometries have been realized on the same AlGaAs/GaAs heterojunction. Under the same operating conditions with a power consumption of 30?μW, experimental results at 4.2?K and low frequency range show that the input voltage noise is almost inversely proportional to the square root of the input capacitance: a noise value as low as $0.46~\mathrm{nV}/\sqrt{\mathrm{Hz}}$ at 1?kHz has been obtained with an input capacitance of about 100?pF.     

Electrical and photocurrent characteristics of Au/PVA (Co-doped)/n-Si photoconductive diodes

In this work, we investigate the some main electrical and photocurrent properties of the Au/PVA(Co-doped)/n-Si diodes by using current–voltage (I–V) measurements at dark and various illumination intensity. Two types of diodes with and without polyvinyl alcohol (PVA) (Co-doped) polymeric interfacial layer were fabricated and measured at room temperature. Results show that the polymeric interfacial layers and series resistance (R_s) strongly affect the main electrical parameters of these structures. Also, metal/polymer/semiconductor (MPS) diode with PVA (Co-doped) interfacial organic layer is very sensitive to the light such that the current in reverse bias region increase by 10³–10⁴ times with the increasing illumination intensity. The open circuit voltage V_oc and short-circuit current I_sc values of this MPS diode under 100 mW/cm² illumination intensity were found as 0.28 V and 19.3 μA, respectively.     

Thin film CdZnS/CuInSe2 solar cells by spray pyrolysis

Cd_1−xZn_xS/CuInSe₂ solar cells having efficiencies in the range of 2·3% were fabricated by spray pyrolysis. The best cell had the following parameters:V _oc = 305 mV,J _sc = 32 mA/cm², FF = 0·32 area = 0·4 cm² and efficiency = 3·149%.V _oc versus temperature measurements showed that the electron affinity difference was 0·22 eV. Forward dark current versus voltage curves were plotted and a possible current mechanism occurring in these cells has been proposed.     

All-chemically deposited Bi2S3/PbS solar cells

We report on solar cells with a cross-sectional layout: TCO/window/Bi₂S₃/PbS, in which a commercial SnO₂ transparent conductive oxide (TCO-PPG Sungate 500); chemically deposited window layers of CdS, ZnS or their oxides; n-type Bi₂S₃ (100 nm) and p-type PbS (360-550 nm) absorber films constitute the cell structures. The crystalline structure, optical, and electrical properties of the constituent films are presented. The open circuit voltage (V_oc) and short-circuit current density (J_sc), for 1000 W/m² solar radiation, of these solar cells depend on the window layers, and vary in the range, 130-310 mV and 0.5-5 mA/cm², respectively. The typical fill factors (FF) of these cells are 0.25-0.42, and conversion efficiency, 0.1-0.4%.     

Electrical properties of anisotype n-TiN/p-Hg3In2Te6 heterojunctions

Photosensitive anisotype n-TiN/p-Hg₃In₂Te₆ heterojunctions have been obtained by reactive magnetron sputtering of thin n-type titanium nitride (TiN) films onto single-crystalline plates of p-type Hg₃In₂Te₆. It is established that the obtained heterostructures generate an open-circuit voltage of V _oc = 0.52 V and a short-circuit current density of I _sc = 0.265 mA/cm² with a filling factor of FF = 0.39 under illumination at a power density of 80 mW/cm².     

Aligning Solution‐Derived Carbon Nanotube Film with Full Surface Coverage for High‐Performance Electronics Applications

The main challenge for application of solution‐derived carbon nanotubes (CNTs) in high performance field‐effect transistor (FET) is how to align CNTs into an array with high density and full surface coverage. A directional shrinking transfer method is developed to realize high density aligned array based on randomly orientated CNT network film. Through transferring a solution‐derived CNT network film onto a stretched retractable film followed by a shrinking process, alignment degree and density of CNT film increase with the shrinking multiple. The quadruply shrunk CNT films present well alignment, which is identified by the polarized Raman spectroscopy and electrical transport measurements. Based on the high quality and high density aligned CNT array, the fabricated FETs with channel length of 300 nm present ultrahigh performance including on‐state current I_on of 290 µA µm^?1 (V_ds = ?1.5 V and V_gs = ?2 V) and peak transconductance g_m of 150 µS µm^?1, which are, respectively, among the highest corresponding values in the reported CNT array FETs. High quality and high semiconducting purity CNT arrays with high density and full coverage obtained through this method promote the development of high performance CNT‐based electronics.     

50 nm metamorphic GaAs and InP HEMTs

This paper reviews some of the recent work at the Nanoelectronics Research Centre at the University of Glasgow on the optimisation of 50 nm metamorphic GaAs and InP HEMTs. Typical DC and RF figures of merit obtained from 50 nm metamorphic GaAs HEMTs include I_dss of 800 mA/mm, g_m of 1100 mS/mm, threshold voltage standard deviation of 5 mV across a 25 mm × 25 mm area, f_T of 440 GHz and f_max of 400 GHz, all at a drain bias of 1.0 V. To our knowledge, these are the highest operating frequency GaAs-based transistors to date. At V_d = 0.8 V and V_g = − 0.6 V, a NF_min and G_ass of 0.7 dB and 13 dB respectively at 26 GHz have been demonstrated.For similar geometry InP HEMTs, DC and RF figures of merit are the following: I_dss of 900 mA/mm, g_m of 1600 mS/mm, f_T of 550 GHz, f_max of 440 GHz, and NF_min and G_ass of 0.9 dB and 14 dB respectively at 26 GHz. The highest performance 50 nm HEMTs reported to date. Using these technologies, single stage MMMICs with gain of at least 7 dB and a return loss of better than − 5 dB across a 24 GHz bandwidth from 71 GHz to 95 GHz have been realised. Noise figure of 2.5 dB and associated gain of 7.3 dB at 90 GHz have been achieved with a DC power consumption of 20 mW.     

An Approach to Use a Raw Single Crystal Whisker as Intrinsic Josephson Junctions Stack

We have developed a technique to observe the intrinsic Josephson effect in Bi₂Sr₂CaCu₂O_8+δ (Bi-2212) single crystal whiskers. In this technique, a raw Bi-2212 single crystal whisker used as intrinsic Josephson junctions (IJJs) along the c-axis. The technique is simple, quick, and less-cost processing. First, a whisker made to stand on ac-plane and then two electrodes were made in ab-planes on either side. The standing whisker with this configuration worked as IJJs. The standing whisker (1.6 mm×40 μm×3 μm) showed the transition temperature of about 84 K. The critical current was about 15 mA at 8 K (critical current density ～23 A/cm²). We observed voltage gap of about 500 mV in current–voltage (I–V) characteristics. This corresponds to a few hundred of IJJs out of ～2,000 IJJs in the whisker thickness. Observations reflect that the technique can be further improved with the single crystal quality, shape of single crystal whisker, and annealing conditions.     

Chemically deposited lead sulfide and bismuth sulfide thin films and Bi2S3/PbS solar cells

Solar cells with a short-circuit current density (J_sc) of 6 mA/cm², an open circuit voltage (V_oc) of 280 mV and a conversion efficiency of 0.5% under a 1000 W/m² solar radiation were prepared by sequential chemical deposition of Bi₂S₂ (160 nm) and PbS (400 nm) thin films. The optical band gap (E_g) of Bi₂S₃ (160 nm) decreased from 1.67 to 1.61 eV upon heating the as-deposited film at 250 °C in air for 15 min to make it crystalline, but also reduced its thickness to 100 nm. Photoconductivity of this film is 0.003 (Ω cm)^− 1. The E_g of PbS film (200 nm) deposited at 25 °C (24 h) is 0.57 eV, and is 0.49 eV for the film deposited at 40 °C. The electrical conductivity of the latter is 0.48 (Ω cm)^− 1. The photo-generated current density for a Bi₂S₃(100 nm)/PbS(300 nm) absorber stack is above 40 mA/cm² under AM 1.5 G (1000 W/m²) solar radiation. However, the optical losses in the cell structure reduces the J_sc. Spectral sensitivity of the external quantum efficiency of the cell establishes the contribution of Bi₂S₃ and PbS to J_sc. The energy level diagram of the cell structure suggests a built-in potential of 470 mV for the present case. Six series-connected cells gave the V_oc of 1.4 V and J_sc of 5 mA/cm².     

Power Law Dependence of I?CV Characteristics of Bi-2212 Whiskers at Low Magnetic Fields

In this study, BiSrCaCuO superconducting whiskers were fabricated by using a glass-ceramics process. The T _c value of the whiskers fabricated was found to be 90.2?K. I?CV characteristics of the whiskers were studied in the temperature range of 10?C70?K under low magnetic fields. The transport critical current density of whiskers was calculated between 19 and 0.63??10⁴ A/cm² at 10?C60?K. I?CV data were fitted using the Levenberg?CMarquardt technique. Results were discussed and so was their dependence on magnetic and electrical properties of the superconductors.     

Solar cells with Sb2S3 absorber films

CdS/Sb₂S₃/PbS structures were prepared by sequential chemical deposition of CdS, Sb₂S₃ and PbS thin films on TEC-8 (Pilkington) transparent electrically conductive SnO₂ (TCO) coatings. CdS thin films (100 nm) were deposited with hexagonal structure from Cd-citrate bath and of cubic structure from Cd-ammine/triethanolamine bath. Sb₂S₃ thin films were deposited at 40 °C from a solution mixture of potassium antimony tartrate, triethanolamine, ammonia and thioacetamide(TA) or at 1 to 10 °C from a mixture of antimony trichloride and thiosulfate (TS). These films were made photoconductive by heating at temperatures 250 to 300 °C. When heated in the presence of a chemically deposited Se thin film of 300 nm, a solid solution Sb₂S_1.8Se_1.2 resulted. PbS thin films of 100-200 nm thickness were deposited on the TCO/CdS/Sb₂S₃ or TCO/CdS/Sb₂S_1.8Se_1.2 structure. Graphite paint was applied on the PbS film prior to applying a silver epoxy paint. The cell structures were of area 0.4 cm². The best results reported here is for a cell: TCO/CdS(hex-100 nm)/Sb₂S₃(TS-100 nm)/PbS(200 nm) with open circuit voltage (V_oc) 640 mV, short circuit current density 3.73 mA/cm², fill factor 0.29, and conversion efficiency 0.7% under 1000 Wm^− 2 sunlight. Four series-connected cells of area 1 cm² each gave V_oc of 2 V and short circuit current of 1.15 mA.     

Fabrication of n-type Schottky barrier thin-film transistor with channel length and width of 0.1 μm and erbium silicide source/drain

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, I_ON/I_OFF ratio of 5.8 × 10⁴ and I_ON of 2 μA/µm at V_G = 3 V, V_D = 2.5 V for 0.1 μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.     

Development of Ultra-Low Noise HEMTs for Cryoelectronics at ≤4.2 K

We report on DC and noise characteristics at 4.2 K of High Electron Mobility Transistors (HEMTs) which have been realized at LPN/CNRS. This work is aimed to develop high performance, low-power, low-frequency noise and low-temperature field-effect transistors for the future cryoelectronics. A high quality two-dimensional electron gas (2DEG) based on AlGaAs/GaAs heterostructure has been used to realize appropriately designed HEMTs with different gate configurations. With these transistors, we have obtained, for example, a transconductance of about 100 mS and a voltage gain of 26 with a power dissipation of less than 100 μW at 4.2 K; and a corresponded equivalent input voltage noise of 1.2 nV/Hz^1/2 at 1 kHz and as low as 0.12 nV/Hz^1/2 at 100 kHz.