Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Suppression of overtone oscillation and low‐current operation using novel‐design scheme for quartz crystal oscillators

A novel design is proposed for a low‐frequency quartz crystal oscillator circuit. Negative resistance in a low‐frequency CMOS‐inverter quartz oscillator was reviewed for the fundamental mode at 32 kHz and the overtone oscillation at 200 kHz. Suppression of the overtone oscillation, appropriate gain, and drive current reduction are realized by adding only three circuit components. Experimental results and an estimate of the absolute value of the negative resistance are presented for the conventional Colpitts circuit and two types of the quartz crystal oscillator circuit. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

FDCCII‐based electronically tunable voltage‐mode biquad filter

In this work, a voltage‐mode biquad filter realizing low‐pass, band‐pass and high‐pass characteristics is presented. The proposed filter, which employs two FDCCIIs, two grounded capacitors and two NMOS transistors, provides electronic tunability with the control voltage applied to the gate. NMOS transistors act as linear resistor. Furthermore, the proposed circuit still enjoys realization using a low number of active and passive components, no requirement with the component choice conditions to realize specific filtering functions, high input impedance, and low active and passive sensitivities performance. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

Four‐segment oscillator circuit for piezoelectric sensing devices

Novel circuit design is proposed for a low‐frequency quartz crystal oscillator circuit that consists of four segments. The characteristics of the negative resistance in a low‐frequency Complementary Metal Oxide Semiconductor (CMOS)‐inverter quartz oscillator were reviewed for the two modes of SC (stress‐compensated) cut mode and the overtone of low‐frequency mode; separation of two modes and suppression of overtone oscillation were demonstrated successfully. Experimental results and an estimate of the absolute value of the negative resistance are presented for the four‐segment oscillator circuit and the conventional Colpitts circuit and two new types of oscillator circuits. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel three‐phase converter using a three‐phase series chopper

This paper proposes a novel three‐phase converter using a three‐phase series chopper. The proposed circuit is composed of three switching devices, three‐phase diode bridge, input reactors, and LC low‐pass filter. In the conventional circuit, which combines three‐phase diode bridge and boost voltage chopper, to obtain sinusoidal input current the output voltage must be two or three times larger than the maximum input line voltage. However, in the proposed circuit, the input current can be controlled to be sinusoidal also when the output voltage is the same as the maximum input line voltage. This can be achieved because in the proposed circuit the discharging current of the reactors does not flow through the voltage source. The control method of the proposed circuit is as simple as that of the conventional circuit since all three switching devices are simultaneously turned on and off. This paper discusses the theoretical analysis and the design of the proposed circuit. In addition, simulation and experimental results are reported. The proposed circuit has obtained a 93% efficiency, and 99.7% at 1.3kW load as the input power factor. © 2000 Scripta Technica, Electr Eng Jpn, 132(4): 79–88, 2000     

Subharmonic injection‐locking and self‐oscillating mixing

Subharmonic injection‐locking and self‐oscillating mixing functions of a modified Colpitts oscillator operating at 1 GHz are reported. The injection‐locking circuit, using a GaAs FET, is described theoretically and experimentally. Phase noise, power consumption and conversion gain measurements indicate that the proposed design is attractive for low‐cost, low‐power consumption front‐ends. Copyright © 2008 John Wiley & Sons, Ltd.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

Memristor‐based voltage‐controlled relaxation oscillators

This paper introduces two voltage‐controlled memristor‐based reactance‐less oscillators with analytical and circuit simulations. Two different topologies which are R‐M and M‐R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor‐based voltage‐controlled oscillator (VCO) is introduced as an application for the proposed circuits which is nano‐size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.     

A single‐stage high power‐factor bridgeless AC‐LED driver for lighting applications

An alternating‐current light‐emitting diode (AC‐LED) driver is implemented between the grid and lamp to eliminate the disadvantages of a directly grid‐tied AC‐LED lamp. In order to highlight the benefits of AC‐LED technology, a single‐stage converter with few components is adopted. A high power‐factor single‐stage bridgeless AC/AC converter is proposed with higher efficiency, greater power factor, less harmonics to pass IEC 61000‐3‐2 class C, and better regulation of output current. The brightness and flicker frequency issues caused by a low‐frequency sinusoidal input are surpassed by the implementation of a high‐frequency square‐wave output current. In addition, the characteristics of the proposed circuit are discussed and analyzed in order to design the AC‐LED driver. Finally, some simulation and experimental results are shown to verify this proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

A small fully digital open‐loop clock and data recovery circuit for wired BANs

This paper proposes a new open‐loop and low complexity (small size) fast‐lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open‐loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase‐locked loops or delay‐locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non‐return‐to‐zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal‐oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35‐data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

CMOS‐controlled inverting CDBA with a new all‐pass filter application

In this study, new active elements called inverting current differencing buffered amplifier (ICDBA) and current‐controlled ICDBA (C‐ICDBA) are presented. Unlike current differencing buffered amplifier (CDBA), their voltage transfer ratio between the Z and W terminals are equal to minus one. Furthermore, CMOS implementations of the C‐ICDBA and current‐controlled CDBA (C‐CDBA) are shown. Moreover, a novel first‐order all‐pass filter is proposed to show advantages and new circuit producing capability of the ICDBA/C‐ICDBA. Lastly, an electronically tunable band‐pass filter is given as an application example using the presented all‐pass filter. The measured and simulation results are in good agreement with the theoretical ones. Copyright © 2010 John Wiley & Sons, Ltd.     

Memristor‐based pseudo‐random pattern generator using relaxation oscillator

This letter presents a new pseudo‐random pattern generator using a memristor and relaxation oscillator based on an operational amplifier. The pulse width of the proposed generator is determined by the resistance storage property of the memristor, and the random pulse sequence depends on the RC time constant of the relaxation oscillator. From the simulation results, we show that the pulse width time is 7.6 μ s, and the random pulse sequence is 2048 bits. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

All‐pass sections with rich cascadability and IC realization suitability

In this paper, two new circuit configurations for realizing voltage‐mode (VM) all‐pass sections (APSs) are presented. The proposed circuits employ only two differential voltage current conveyors (DVCCs) and are cascadable with other VM circuits due to their high‐input and low‐output impedances. The first configuration uses a grounded resistor and a grounded capacitor without requiring matching constraints, whereas the second employs two grounded resistors and a grounded capacitor with a single matching condition. While the first configuration can realize only one all‐pass response, the second can provide inverting and non‐inverting all‐pass responses with selection of appropriate input port. Adding two grounded resistors to the proposed filters, variable gain APSs can also be obtained. As applications, two quadrature oscillators, each of which using one of the proposed all‐pass circuits, one grounded resistor and one grounded capacitor are presented. SPICE simulation results are included to verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

Stability analysis of wideband linear bipolar varactor‐controlled oscillator with two‐coupled resonant circuits

Theoretical analysis of the stability conditions of the steady‐state operation modes and tuning bandwidth characteristics of bipolar self‐biased varactor‐controlled oscillator (VCO) with two‐coupled resonant circuits are presented. The recommendations at the choice of the circuit and varactor parameters for a linearization of the wideband tuning frequency characteristics under free‐running stable oscillation conditions are given. Highly linear octave‐band tuning operation was found to be possible using hyper‐abrupt varactors in two‐coupled resonant circuits VCO. Numerical and experimental results verify the validity of the design approach described. Copyright © 1999 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.