Non-linear optimization with constraints: A cook-book approach

Based on the stationary co-content theorem in non-linear circuit theory and the penalty function approach in non-linear programming theory, a canonical circuit for simulating general non-linear programming problems with equality and/or inequality constraints has been developed. the task of solving a non-linear optimization problem with constraints reduces to that of finding the solution of the associated canonical circuit using a circuit simulation program, such as SPICE. A catalogue of canonical circuits is given for each class of non-linear programming problem. Using this catalogue, an engineer can solve non-linear optimization problems by a cook-book approach without learning any theory on non-linear programming. Several examples are given which demonstrate how SPICE can be used, without modification, for solving linear programming problems, quadratic programming problems, and polynomial programming problems.     

Central suboptimal H∞ filter design for nonlinear polynomial systems

This paper presents the central finite‐dimensional H_∞ filter for nonlinear polynomial systems, which is suboptimal for a given threshold γ with respect to a modified Bolza–Meyer quadratic criterion including the attenuation control term with the opposite sign. In contrast to the previously obtained results, the paper reduces the original H_∞ filtering problem to the corresponding optimal H₂ filtering problem, using the technique proposed in (IEEE Trans. Automat. Control 1989; 34 :831–847). The paper presents the central suboptimal H_∞ filter for the general case of nonlinear polynomial systems based on the optimal H₂ filter given in (Int. J. Robust Nonlinear Control 2006; 16 :287–298). The central suboptimal H_∞ filter is also derived in a closed finite‐dimensional form for third (and less) degree polynomial system states. Numerical simulations are conducted to verify performance of the designed central suboptimal filter for nonlinear polynomial systems against the central suboptimal H_∞ filter available for the corresponding linearized system. Copyright © 2008 John Wiley & Sons, Ltd.     

Optimal analog active filter design using craziness‐based particle swarm optimization algorithm

Because of the manufacturing constraints, the optimal selection of passive component values for the design of analog active filter is very critical. As the search on possible combinations in preferred values for capacitors and resistors is an exhaustive process, it has to be automated with high accuracy within short computation time. Evolutionary computation may be an attractive alternative for automatic selection of optimal discrete component values such as resistors and capacitors for analog active filter design. This paper presents an efficient evolutionary optimization approach for optimal analog filter design considering different topologies and manufacturing series by selecting their component values. The evolutionary optimization technique employed is craziness‐based particle swarm optimization (CRPSO). PSO is very simple in concept, easy to implement and computationally efficient algorithm with two main advantages: fast convergence and only a few control parameters. However, the performance of PSO depends on its control parameters and may be influenced by premature convergence and stagnation problem. To overcome these problems, the PSO algorithm has been modified to CRPSO and is used for the selection of optimal passive component values of fourth‐order Butterworth low‐pass analog active filter and second‐order state variable low‐pass filter, respectively. CRPSO performs the dual task of efficiently selecting the component values as well as minimizing the total design errors of low‐pass active filters. The component values of the filters are selected in such a way so that they become E12/E24/E96 series compatible. The simulation results prove that CRPSO efficiently minimizes the total design error with respect to previously used optimization techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

A design guideline of parasitic inductance for preventing oscillatory false triggering of fast switching GaN‐FET

Gallium nitride field‐effect transistors (GaN‐FETs) are attractive devices because of its low on‐state resistance and fast switching capability. However, they can suffer from false triggering caused by fast switching. Particularly, a disastrous oscillation of repetitive false triggering can occur after a turn‐off, which may deteriorate the reliability of power converters. To address this issue, we give a design guideline to prevent this phenomenon. We analyze a simple circuit model to derive the condition of occurrence of this phenomenon, which is then verified experimentally. Results show that the parasitic inductance of the gating circuit, L_g, and that of the decoupling circuit, L_d, should be designed so that the LC resonance frequency of L_g and the gate–source capacitance of the GaN‐FET does not coincide with that of L_d and the drain–source capacitance, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An Improved Particle Swarm Optimization for Nonconvex Economic Dispatch Problems

This paper presents an efficient approach for solving economic dispatch (ED) problems with nonconvex cost functions using an improved particle swarm optimization (IPSO). Although the particle swarm optimization (PSO) approaches have several advantages suitable to heavily constrained nonconvex optimization problems, they still can have the drawbacks such as local optimal trapping due to premature convergence (i.e., exploration problem), insufficient capability to find nearby extreme points (i.e., exploitation problem), and lack of efficient mechanism to treat the constraints (i.e., constraint handling problem). This paper proposes an improved PSO framework employing chaotic sequences combined with the conventional linearly decreasing inertia weights and adopting a crossover operation scheme to increase both exploration and exploitation capability of the PSO. In addition, an effective constraint handling framework is employed for considering equality and inequality constraints. The proposed IPSO is applied to three different nonconvex ED problems with valve-point effects, prohibited operating zones with ramp rate limits as well as transmission network losses, and multi-fuels with valve-point effects. Additionally, it is applied to the large-scale power system of Korea. Also, the results are compared with those of the state-of-the-art methods.      

Delay‐dependent robust L2–L∞ filtering of T‐S fuzzy systems with time‐varying delays

This paper considers the problem of robust delay‐dependent L₂–L_∞ filtering for a class of Takagi–Sugeno fuzzy systems with time‐varying delays. The purpose is to design a fuzzy filter such that both the robust stability and a prescribed L₂–L_∞ performance level of the filtering error system are guaranteed. A delay‐dependent sufficient condition for the solvability of the problem is obtained and a linear matrix inequality (LMI) approach is developed. A desired filter can be constructed by solving a set of LMIs. Copyright © 2009 John Wiley & Sons, Ltd.     

Digital filter design with state space method for 1‐bit signal processing based on delta‐sigma modulation

One‐bit signal processing based on delta‐sigma modulation has been studied for hardware implementation of signal processing systems. In the 1‐bit signal processing, finite word‐length problems such as overflow and coefficient quantization error occur. To solve the problems, a new design method with state space is proposed in this paper. Digital filters are designed to show the feasibility of the method. First, the L₁/L₂‐sensitivity is shown to evaluate coefficient quantization error and L₂ scaling constraints to prevent overflow. Second, a state space equation is presented and the L₁/L₂‐sensitivity and L₂‐scaling constraints are extended to take the filter structure and oversampling effects into account. Finally, the proposed method is shown to attain a higher SNR than conventional ones. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 175(4): 48–56, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21075     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

The modified Pascal polynomial approximation and filter design method

Polynomial approximations are extensively used in analog and IIR digital filter design. In this paper, a comprehensive filter design and an optimization procedure are presented explicitly using a filter‐appropriate modified Pascal polynomial. The so‐designed all‐pole Pascal filters exhibit non‐equiripple passband and monotonic transition and stopband responses. The order of the new Pascal filters is calculated from the order inequality which, although it cannot be analytically solved, leads to a nomograph that has been created and is presented here. Inevitably, the mathematical complexity introduced by the nature of the Pascal polynomials makes the analytical expression of the poles of the transfer function unfeasible and for that reason poles are given by means of appropriate tables. The design method is demonstrated in several detailed examples and Pascal filters are compared with their all‐pole counterparts, Butterworth and Chebyshev, over which they reveal certain advantages and disadvantages. Copyright © 2010 John Wiley & Sons, Ltd.     

Fault detection filter design for discrete‐time switched linear systems with mode‐dependent average dwell‐time

This paper is concerned with the problem of the fault detection (FD) filter design for discrete‐time switched linear systems with mode‐dependent average dwell‐time. The switching law is mode‐dependent and each subsystem has its own average dwell‐time. The FD filters are designed such that the augmented switched systems are asymptotically stable, and the residual signal generated by the filters achieves a weighted l₂‐gain for some disturbances and guarantees an H _? performance for the fault. By the aid of multiple Lyapunov functions combined with projection lemma, sufficient conditions for the design of the FD filters are formulated by linear matrix inequalities, furthermore, the filters gains are characterized in terms of the solution of a convex optimization problem. Finally, an application to boost convertor is given to illustrate the effectiveness and the applicability of the proposed design method. Copyright © 2013 John Wiley & Sons, Ltd.     

Optimal design of lattice wave digital fractional‐order Butterworth filter

This letter presents the design of digital fractional‐order Butterworth filter (DFOBF) of order (n+α) , where n is an integer, and α ∈ (0,1) , from the perspective of optimal realization. The magnitude–frequency characteristic of the DFOBF is optimally modeled using the computationally efficient lattice wave digital filters (LWDFs). Design examples for the third‐ and fifth‐order LWDF‐DFOBFs with various values of n, α_, and cut‐off frequencies are presented.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Recently several topological representations have been explored as alternatives to the conventional absolute‐coordinate representation for integrated circuit layout automation. Those topological representations, however, lack one or more aspects in capturing the solution space subject to symmetry constraints, which are abundant in analog layouts. In this paper, we explore the use of transitive closure graphs (TCGs) to represent analog placements, i.e. placements with symmetry constraints. We define a set of conditions so that a TCG satisfying these conditions, referred to as a symmetric‐feasible TCG, will correspond to a valid symmetric placement and vice versa. We then present an O(n²) algorithm, where n is the number of cells to be placed, to build a symmetric placement from a symmetric‐feasible TCG, a problem known as packing. We further describe a set of random perturbation operations on existing symmetric‐feasible TCGs to generate new symmetric‐feasible TCGs with time complexity of O(n) . This allows our TCG‐based symmetry‐aware analog placer to search only the symmetric‐feasible TCG solution space, leading to a substantial reduction of the search space and solution time. Experimental results on several analog circuits have confirmed the superiority of the TCG representation to the conventional absolute‐coordinate representation as well as several other topological representations in analog layout design. Copyright © 2008 John Wiley & Sons, Ltd.     

Designing globally optimal delta–sigma modulator topologies via signomial programming

We present a design methodology for globally optimizing the topologies of delta–sigma modulators (DSMs). Previous work cast the design task into a general non‐convex, nonlinear programming problem, whereas we propose to recast it as a signomial programming problem. Convexification strategies are presented for transforming the signomial programming problem into its equivalent convex counterpart, thereby enabling the solution of globally optimal design parameters. It is also possible to include circuit non‐ideal effects that affect the transfer function of the modulator into the formulation without affecting the computational efficiency. The proposed framework has been applied to topology synthesis problems of single‐loop and multi‐loop low‐pass DSMs based on discrete‐time circuitry. Numerical results confirm the effectiveness of the proposed approach over conventional nonlinear programming techniques. Copyright © 2008 John Wiley & Sons, Ltd.     

Optimization of multiobjective system reliability design using FLC controlled GA

A practical optimal reliability design of a system requiring high system reliability could be formulated as an appropriate mathematical programming model; however, in the real world, we should be concerned with some kinds of decision criteria. In particular, system reliability and construction cost are basically in conflict with each other, so that when taking both of them into consideration, the system reliability design model can be formulated as a bi‐objective mathematical programming model. In this research, we consider a bi‐criteria redundant system reliability design problem which is optimized by selecting and assigning system components among different valuable candidates for constructing a series‐parallel redundant system. Such a problem is formulated as a bi‐criteria nonlinear integer programming (bi‐nIP) model. In the past decade, several researchers have developed many heuristic algorithms including genetic algorithms (GAs) for solving multi‐criteria system reliability optimization problems and obtained acceptable and satisfactory results. Unfortunately, the Pareto solutions obtained by solving a multi‐objective optimization problem using a GA cannot guarantee its quality, and the number of Pareto solutions obtained is sometimes small. In order to overcome such problems, we propose a hybrid genetic algorithm combined with a Fuzzy Logic Controller (FLC) and a local search technique to obtain as many Pareto solutions and as good as possible. The efficiency of the proposed method is demonstrated through comparative numerical experiments. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(3): 72–80, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20319     

Optimal analog‐to‐digital transformation of fractional‐order Butterworth filter using binomial series expansion with Al‐Alaoui operator

This paper deals with the optimal analog‐to‐digital transformation of fractional‐order Butterworth filter (FOBF) in terms of infinite impulse response templates. The fractional‐order transfer function of the analog FOBF is transformed into its digital counterpart by employing the Binomial series expansion of different truncation orders, based on the Al‐Alaoui operator. This nonoptimal solution is then treated as an initial point for a local search optimizer such as the Nelder–Mead simplex (NMS) algorithm and also injected as a super‐fit individual in the initial population of a global search constrained evolutionary optimization algorithm (CEOA). Design stability and minimum‐phase response constraints are formulated for the super‐fit scheme. Both the techniques demonstrate good modeling performance; however, the super‐fit CEOA can markedly outperform the NMS method as the problem dimensionality increases.     

Robust controller design for large interconnected power systems with model uncertainties based on wide-area measurement

Recently the controller using wide-area measurement systems (WAMS) signals has been suggested to accommodate the dynamic performances of large interconnected power systems. However, there is an unavoidable delay before the wide-area signals are received at the controller site. Therefore, a delay-independent robust control problem of large interconnected power systems is studied via H _∞ fuzzy control method based on wide-area measurement. First, a set of equivalent Takagi–Sugeno (T–S) fuzzy model is adopted to represent the nonlinear large interconnected power system. A wide-area state feedback decentralized H _∞ fuzzy control scheme is developed to override the various disturbances, solve the effect of model uncertainties and stabilize the large power system. The H _∞ decentralized control problem is parameterized in terms of a linear matrix inequality (LMI) problem, and the LMI problem can be solved efficiently using convex optimization techniques. Finally, the effectiveness of the proposed controller design methodology is demonstrated through simulation example. This work is supported by the National Science Foundation of China under grant 60374039, 60404007.     

Switched‐capacitor‐voltage‐multiplier boost DC–AC inverter with adaptive stages

A multistage switched‐capacitor‐voltage‐multiplier inverter (SCVMI) is proposed with a variable‐conversion‐ratio phase generator and a sinusoidal pulse‐width‐modulation controller for boost DC–AC conversion and high‐efficiency regulation. Its power unit contains: SCVM booster and H‐bridge. The SCVM booster includes two m_c‐stage switched‐capacitor cells and two n_c‐stage switched‐capacitor cells in the interleaving operation to realize DC–DC boost gain of m_c × n_c at most. Here, the variable‐conversion‐ratio phase generator is suggested and adopted to change the running stage number and topological path for a suitable gain level of m × n (m = 1, 2, ?,m_c, n = 1, 2, ?,n_c) to improve efficiency, especially for the lower AC output. The H‐bridge is employed for DC–AC conversion, where four switches are controlled by sinusoidal pulse‐width‐modulation not only for full‐wave output but also for output regulation as well as robustness to source/loading variation. Some theoretical analysis and design include: SCVMI model, steady‐state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, output filter, and control design. Finally, the closed‐loop SCVMI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of this scheme. Copyright © 2011 John Wiley & Sons, Ltd.