Design of efficient QCA multiplexers

A new methodology to realize efficient multiplexers using quantum‐dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan‐in, by adding in the worst‐case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. Copyright © 2015 John Wiley & Sons, Ltd.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

A simple and accurate dynamical modeling of quantum‐dot semiconductor optical amplifiers

In this article, quantum‐dot semiconductor optical amplifiers (QD‐SOAs) have been modelled using state space method. To derive this model, we have manipulated the rate equation model of the QD‐SOA, where the average values of the occupation probabilities along the QD‐SOA cavity are considered as the state variables of the system. Using these variables, the distance dependence of the rate equations is eliminated. The derived state space model gives the optical gain and output signal of the amplifier with a high accuracy. Simulation results show that the derived model is not only much simpler and faster than conventional rate equation models, but also the optical gain and output signal of the investigated QD‐SOA are calculated with a higher precision compared to the rate equation model. Copyright © 2013 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Design and research of a three‐phase voltage sensor based on D‐dot principle

In the design of three‐phase D‐dot voltage sensor based on electric field coupling, both effects of both the adjacent phase electric fields and distribution parameters on measurement should be taken into consideration. This paper builds a simulation model and a physical measuring system of a three‐phase sensor, measures the effect of the distribution parameters by the simulation model, and finally finds the transfer function between the input and output voltage signals of the circuit. The measured voltage waveforms and parameters can be reflected by the physical measuring system. Our results provide a theoretical basis for the design of a three‐phase D‐dot voltage sensor. And the measuring system can achieve multipoint synchronous acquisition and ensure less distortion. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Verification of 1D BJT numerical simulation and its application to mixed‐level device and circuit simulation

In this paper, we study on a 1D BJT model, which saves the memory size and computation time and verify that the characteristic of 1D BJT model is in good agreement with 2D BJT model. We use the equivalent circuit approach to simulate the BJT device. Poisson's equation and continuity equations for electron and hole are formulated into a subcircuit format suitable for general circuit simulator in the equivalent circuit approach. In order to solve the 2D device simulation, the simulation environment needs a powerful solver. So we use the band matrix solver to replace the full matrix solver. But the 2D BJT simulation still needs a large computation time, so we must develop the efficient 1D BJT model. In 1D BJT simulation, we have overcome the base boundary condition and verified that the base boundary conditions in 1D BJT model closely approach to that in 2D BJT model. Finally, we apply it to two applications and study the operation concepts of these applications. Copyright © 2002 John Wiley & Sons, Ltd.     

Performance evaluation and experimental analysis of a novel single‐phase brushless PM motor

In order to equip the single‐phase brushless permanent magnet (PM) motor with self‐starting capability without a complex structure, we present a new kind of asymmetric air‐gap topology which can lead to the d‐ , q ‐axis magnetic circuit asymmetry of the motor. The field‐circuit‐coupling finite element method simulation model of the proposed motor controlled with a constant V / f control is built by using the 2D Maxwell software. The geometric parameters of the motor are also optimized by changing pole arc ratio of the PM (α_p ) and its eccentricity (e ), and the operational characteristic is investigated. Finally, an experimental platform of the prototype and its control system are set up. Performance comparison of the experimental results and simulation results of the proposed motor running in various operating modes is reported. All the results show that the asymmetric air‐gap single‐phase brushless PM motor has potential to be used in the household appliances. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A closed‐form equation approach to multi‐port/multi‐zone behavioral modeling of GaN FET Amplifiers

In this paper, a systematic method for the simulation of weakly and mildly nonlinear GaN FET amplifiers is reported. The core of the proposal is a third‐order Volterra‐based behavioral model with multi‐spectral and multi‐node capabilities that is formally derived from a circuit‐level representation. Starting with the equivalent circuit of a typical FET device with thermal power feedback and fading memory, described in terms of its large‐signal functions, closed‐form expressions for the kernels at the gate, drain and thermal nodes are developed up to the third order. The use of these kernels allows the calculation of the responses in the dc, first‐, second‐ and third‐harmonic zones, which are shown to be dependent on the frequency response of the amplifier circuit terminating impedances and thermal filter. The simulation approach has been applied to calculate the nonlinear response of a typical power amplifier circuit, showing the ability of the proposed approach to provide an accurate prediction of multi‐spectral, multi‐node, multi‐bias characteristics, including AM/AM‐AM/PM conversion, spectral regrowth, intermodulation, and temperature rise, under diverse input signal waveforms and bandwidths. These results have been successfully compared with commercial CAD tools based on harmonic balance or envelope simulation. Copyright © 2014 John Wiley & Sons, Ltd.     

Efficient optimization‐oriented design methodology of high‐order 3‐D filters using 2‐D and 3‐D electromagnetic simulators

This paper proposes a computationally highly efficient interface between two‐dimensional (2‐D) and three‐dimensional (3‐D) electromagnetic (EM) simulators for the optimization‐oriented design of high‐order 3‐D filters. In a first step, the novel optimization‐oriented design methodology aligns the 3‐D EM simulator response with the 2‐D EM simulator response of a low‐order 3‐D filter by using an inverse linear space mapping optimization technique. Then, a second mapping performs a calibration with the optimal 2‐D and 3‐D design parameters obtained from the first mapping. The optimization of high‐order filters is carried out using only the efficient 2‐D EM simulator, and the calibration equations directly give the design parameters of the 3‐D filter. The potential and the effectiveness of the proposed optimization‐oriented design methodology are demonstrated through the design of C‐band 3‐D evanescent rectangular waveguide bandpass filters with increasing orders from three to eight. Copyright © 2014 John Wiley & Sons, Ltd.     

Application of a modular multilevel cascade converter (MMCC‐SDBC) to a STATCOM. Control of active power and negative‐sequence reactive power

This paper presents the application of a modular multilevel cascade converter based on single‐delta bridge‐cells (MMCC‐SDBC) to a STATic synchronous COMpensator (STATCOM), particularly for negative‐sequence reactive‐power control. The SDBC is characterized by cascade connection of multiple single‐phase H‐bridge (or full‐bridge) converter cells per leg, which facilitates ?exible circuit design, low voltage steps, and low electromagnetic interference (EMI) emissions. However, there is no published report on such a STATCOM with experimental veri?cation or a control strategy. This paper designs, constructs, and tests a 100‐V 5‐kVA PWM STATCOM based on the SDBC with focus on the operating principle and performance. Experimental results con?rm that this converter can control not only the positive‐sequence reactive power but also the negative‐sequence reactive power and low‐frequency active power intended for the ?icker compensation of arc furnaces. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 183(4): 33–44, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22365     

Design of experiments (DOE) technique for microwave/millimeter wave flip‐chip optimization

We present a design of experiments (DOE) technique for microwave/millimeter wave flip‐chip characterization and optimization. Two optimization approaches, signal bump misalignment and transmission line compensation, are combined together for optimal performance for high frequency operation. First, the design of experiments method is presented and its advantages are emphasized. Then, the two techniques are combined together in a factorial experiment with the purpose of optimizing the return loss to any desired frequency. The experiment is based on test structure fabrication and measurements. The one‐factor‐at‐a‐time strategy shows that return loss performance is increased with the misalignment values and decreased with compensation for the frequency range of interest. However, the statistical analysis revealed that the optimal performance is achieved for maximum compensation, and minimum misalignment. The optimal structure is measured from 1 to 75 GHz and shows return loss better than 17 dB. The method can be extended to include more optimization factors in different analysis intervals. Copyright © 2003 John Wiley & Sons, Ltd.     

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

This paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley & Sons, Ltd.     

Proposal of a cannibalism bug‐based search strategy using genetic algorithms (C‐BUGS) and its application to multiobjective optimization problems

For decision support under a multiobjective environment, it is effective to offer a Pareto optimal solution set with uniform distribution to the decision‐maker. In this paper, a new optimization method for obtaining a Pareto optimal solution set with such uniform distribution is proposed. In order to overcome the difficulty of realizing this goal, the concept of cannibalism is introduced in BUGS (a bug‐based search strategy using genetic algorithms). Introducing the concept of cannibalism achieves the uniform distribution of Pareto optimal solutions. A numerical experiment using typical continuous and discrete multiobjective optimization problems clarifies the usefulness of the proposed method. © 2002 Scripta Technica, Electr Eng Jpn, 139(1): 51–64, 2002; DOI 10.1002/eej.1146     

Takahiro Jibiki,Wataru Fujii,Yasuhiro Tanaka,Development of connection systems for wind power generating plant to electric power network: Experiment at the Tomamae Winvilla power plant,IEEJ Transactions on Electrical and Electronic Engineering (2007)2(1)3‐7

The original article to which this erratum refers was published in the IEEJ Transactions on Electrical and Electronic Engineering IEEJ Trans Elec Electron Eng(2007) 2(1) 3