Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Modern RF front‐ends require wide tuning‐range oscillators with quadrature outputs. In this paper we present a two‐integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm², leading to a figure‐of‐merit FOMA of ?176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis of mismatch impact on image rejection ratio for passive polyphase filters

Passive polyphase filters (PPFs) are useful symmetric RC networks for processing analog quadrature signals. Passive polyphase filters are also used to implement differential‐quadrature or quadrature‐differential converters. The quality of these quadrature signals is essential to achieve good performance in modern communication systems. However, mismatch effects can produce notable degradation in the PPF frequency response, and this results in an important reduction in quadrature signal quality, being amplitude balance and phase offset notably affected. Both these errors could be summarized and evaluated together considering image rejection ratio as a figure of merit. This work deepens in the analysis of mismatch impact on PPF, studying image rejection ratio degradation for 2 PPF types, and a systematic method is proposed to obtain the worst case of mismatch in PPFs with any number of stages. It has been validated in a 65‐nm CMOS technology.     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

Ring oscillator structures with explicitly separated nonlinearity

In this letter, we propose RC and LC nonlinear sinusoidal ring oscillator structures which can also generate subsidiary quadrature outputs. A tanh(x) nonlinearity is employed and is explicitly separated from the oscillators' linear building block (a first‐order all‐pass filter). Numerical and spice simulation results are given. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of ultra low‐power RF oscillators based on the inversion coefficient methodology using BSIM6 model

This paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient (IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade‐off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross‐coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

The effect of parameter mismatches on the output waveform of an LC‐VCO

The effect of parameter mismatches on the output waveforms of a popular voltage‐controlled oscillator is investigated, schematizing the circuit as a system of two mutually coupled oscillators, whose describing equations are derived in a perturbation form. The circuit is studied using the method of two time‐scales showing the existence of synchronization phenomena leading in presence of mismatches to a locking frequency, which significantly differs from the natural frequencies of the tanks, and to an oscillation amplitude different from that of the symmetric case. We also show that in‐phase and quadrature oscillations at the drain nodes can be generated with a proper parameter setting. Circuit simulations confirm the presence of a synchronized oscillation, which is consistent with the prediction of the presented analysis. Copyright © 2009 John Wiley & Sons, Ltd.     

CMOS digitally programmable quadrature oscillators

CMOS digitally programmable quadrature oscillators based on digitally controlled current followers and voltage followers are proposed. The proposed designs provide the advantage of programmability similar to the operational transconductance amplifier‐based oscillators while offering improved linearity. In mixed analog/digital systems, the digital tuning feature allows direct interfacing with the digital signal processing part. Novel realizations that provide both voltage‐mode and current‐mode quadrature sinusoidal signals are presented. Employing only grounded capacitors the designs achieve independent control of the frequency and condition of oscillation that can be tuned digitally. Experimental results obtained from a 0.35 µm CMOS chip fabricated using standard CMOS process are given. Copyright © 2008 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade‐off between gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small‐signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright © 2006 John Wiley & Sons, Ltd.     

Fully nonlinear oscillator noise analysis: an oscillator with no asymptotic phase

Oscillators exist in many systems. Detailed and correct characterization and comprehension of noise in autonomous systems such as oscillators is of utmost importance. Previous approaches to oscillator noise analysis are based on some kind of perturbation analysis, some linear and some nonlinear. However, the derivations of the equations for perturbation analysis are all based on information that is produced by a linearization of the oscillator equations around the periodic steady‐state solution, where it is assumed that the oscillator is orbitally stable and it has the so‐called asymptotic phase property. In this paper, we first discuss these notions from a qualitative perspective, and demonstrate that the asymptotic phase property is crucial in validating all of the previous approaches. We then present the case of a simple oscillator that is orbitally stable but without asymptotic phase, for which previous approaches fail. We then present a fully nonlinear noise analysis of this oscillator. We derive and compute nonlinear, non‐stationary and non‐Gaussian stochastic characterizations for both amplitude and phase noise. We arrive at results that are distinctly different when compared with the ones obtained previously for oscillators with asymptotic phase. We compare and verify our analytical results against extensive Monte Carlo simulations. Copyright © 2006 John Wiley & Sons, Ltd.     

Synchronous and asynchronous operation in dual‐band VCOs

We present a comprehensive analysis of the asynchronous and synchronous operations of fourth‐order oscillators underlying dual‐band voltage‐controlled oscillators. We analyze the occurrence of the self‐synchronization phenomenon (internal resonance) if the ratio of normal frequencies is nearly a ratio of integers, which is 1:3 in the cubic approximation of the nonlinear oscillator characteristic. In this case, we have the simultaneous presence of 2 oscillations with a frequency ratio 1:3, which was demonstrated to be very effective in generating high‐frequency signals in mm‐wave range. The analysis is carried out by developing an analytical approach relying on the averaging principle, as it follows the van der Pol method. The averaging equations, derived simply by a quadrature, allow us to analyze easily the stationary and transient oscillations, and their stability, both in asynchronous and synchronous operations. Expressions for the amplitudes and phases were derived for a cubic nonlinearity and verified by Spice simulations.     

Analytical comparison of reversed nested Miller frequency compensation techniques

In this paper, novel and previously proposed reversed nested Miller compensation (RNMC) networks are analyzed and compared, and their design equations are also presented. Hence, this paper is the natural extension of a previous paper by the authors (Int. J. Circ. Theor. Appl. 2008; 36 (1):53–80), where only the nested Miller compensation topologies were treated. In particular, a coherent and comprehensive analytical comparison of the RNMC topologies, including two new networks presented for the first time, is performed by means of the figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin (Int. J. Circ. Theor. Appl. 2008; 36 (1):53–80). The analysis shows that there is no unique optimal solution among the RNMC topologies, as this depends on the load condition as well as on the relative transconductance magnitude of each amplifier stage. From this point of view, the proposed comparison also outlines useful design guidelines for the optimization of large‐signal and small‐signal performance. Simulations confirming the effectiveness of the proposed design methodology and analytical comparison are also included. Copyright © 2009 John Wiley & Sons, Ltd.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.