A novel circuit element and its application in signal amplification

A novel IC‐based current amplifier configuration for signal‐processing applications that can be configured using commercially available integrated circuit elements is presented. The circuit is accurate, has a wide bandwidth and can drive grounded loads. It utilizes a CCII+ type current conveyor with its input circuit in the feedback loop of a current feedback amplifier (CFA). In the current amplifying mode, the circuit has a low input impedance over a broad frequency range which never rises above the low input impedance of the inverting input of the associated CFA. Experimental results obtained using AD844s confirm the results derived. Copyright © 2007 John Wiley & Sons, Ltd.     

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

Micropower high current‐drive class AB CMOS current‐feedback operational amplifier

A novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley & Sons, Ltd.     

A configuration for realizing floating,linear, voltage‐controlled resistance,inductance and FDNC elements

A configuration using current feedback amplifiers has been presented, which is capable of realizing linear, positive/negative voltage‐controlled resistance, voltage‐controlled inductance and voltage‐controlled frequency‐dependent negative conductance in floating form (and thereby, also in grounded form) from the same structure. The workability of the proposed configuration has been demonstrated by hardware implementation results using AD 844‐type current feedback op‐amps (CFOAs) and BFW‐11‐type JFETs and the workability in high‐frequency range has been demonstrated by SPICE simulation using CMOS CFOAs. Copyright © 2008 John Wiley & Sons, Ltd.     

Class AB amplifier with enhanced slew rate and GBW

The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis,modelling and optimization of a gain boosted telescopic amplifier

In this paper, a thorough analysis of a gain‐boosted telescopic amplifier (GBTA) is presented and a systematic design procedure for optimizing its time response will be given. Specifically, the GBTA closed‐loop time response will be analysed in detail and the constraints eliminating the well‐known ‘slow settling component’ found. Subsequently, an optimization strategy based on the comparison between the GBTA time response and the time response of a pure two‐pole amplifier (referred to as the target system) will be described. This strategy allows the designer to develop a GBTA starting from the target system specifications in a simple and systematic way. The proposed procedure has been validated by means of simulations and excellent agreement found between the simulated and the expected results. Copyright © 2003 John Wiley & Sons, Ltd.     

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.     

On a class of pseudo‐logarithmic amplifiers suitable for use with digitally switched resistors

This paper describes three circuits that implement pseudo‐logarithmic functions, which are simple and easy to implement. The circuits can be realized using operational amplifiers or current feedback amplifiers. Tuning can be achieved using switched resistors, or active resistors, or tunable transconductors, but are best suited for use with digitally switched resistors. Frequency response and stability considerations for two of the circuits are thoroughly discussed and PSPICE results confirming the theoretical results are presented alongside measured results. Copyright © 2007 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

An approach to model high‐frequency distortion in negative‐feedback amplifiers

In this paper, we present an analytical approach to study the harmonic distortion in the frequency domain of operational amplifiers (opamps) embedded in a nonlinear feedback network. The analysis is based on a frequency‐domain block scheme that models the opamp with one block and the feedback network with two blocks, but it is demonstrated that only one feedback block needs to be characterized for the two basic inverting and non‐inverting configurations. The obtained closed‐form expressions extend our understanding of nonlinear frequency behaviour in feedback opamp circuits. Indeed, they give the contribution of each network component to the output distortion. As an instructive example, we analysed second‐ and third‐order harmonic distortion of an active‐RC inverting lossy integrator having all the components nonlinear. The accuracy of the proposed method is confirmed by comparison with computer simulations at transistor level. Copyright © 2006 John Wiley & Sons, Ltd.     

Low-noise and low-sensitivity filters using current-mode coupled biquads

In this paper, it is shown that by adding coupling to biquad pairs to obtain a fourth-order band-pass filter, the output thermal noise is reduced. It is shown analytically that minimum output thermal noise is obtained when the biquads are identical and the negative-feedback factor used for coupling is the same as for the minimum sensitivity to component tolerances and ambient changes. Furthermore, by optimizing the coupled biquads for maximum dynamic range, the output noise is further decreased.     

电测系统中一种信号前处理电路及应用

文中提出一种电流积分式信号前处理电路,可对毫秒级变化的１０＾７￣１０＾－１５Ａ弱电流信号或５ｍＶ￣５０Ｖ电压信号连续线性转换,对１０＾－１２Ａ量级快变弱电信号可实现快速处理。     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.     

High-gain,high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (g_mr₀)⁴ , obtained using a two-stage structure with cascoded stages, and is a two-stage Miller-compensated amplifier employing multipath to remove the positive zero. It has close to rail-to-rail output swing (limited by cascoding) and very low common-mode gain thanks to a replica technique (allowing the use of low-power common-mode feedback [CMFB] loops). Ninety-two decibels of gain and 176 dB of common-mode rejection ratio (CMRR) without CMFB are achieved using a 40-nm complementary metal-oxide semiconductor (CMOS) process. The OTA is used to design a low-power sample-and-hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application.     

Modified CFOA,its transpose,and applications

It is shown that the recently‐proposed modified current feedback operational amplifier (MCFOA) is quite a versatile element in that given a realization for a system function using MCFOAs, we can obtain three alternate realizations using the same MCFOA but by appropriately connecting the y, x, w, and z terminals of the MCFOA to the remaining part of the original realization. Using the results concerning the transpose of a multi‐terminal element, it is further shown that the transpose of an MCFOA is another MCFOA. Thus, using the results of transposition, given a voltage‐mode circuit using MCFOAs, we can directly obtain four current‐mode circuits using the same MCFOAs or vice versa. Copyright © 2015 John Wiley & Sons, Ltd.     

Universal basis for ranking small‐signal aspects of compensation techniques for operational amplifiers

A multi‐pole gain‐bandwidth theorem sets an upper bound to the bandwidth that can be achieved with specified DC gain and external load capacitance, for a given selection of transistors and operating points. A product of the poles and zeros is constrained by ∏(g_m/C) evaluated over the forward‐path active devices. Most practical compensation techniques degrade the actual bandwidth, by factors which the paper explores in detail; depending on the circuit topology, some compensating capacitors can add to the intrinsic device capacitances. A few techniques achieve the ideal. Copyright © 2010 John Wiley & Sons, Ltd.