A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

A scaled 0.25-μm bipolar technology using full e-beamlithography

The full leverage offered by electron-beam lithography has been exploited in a scaled 0.25-μm double polysilicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06 μm. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25-μm emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies     

Surface-micromachined gear trains driven by an on-chipelectrostatic microengine

Test results for a polysilicon, surface-micromachined, electrostatically-actuated microengine driving multiple gears are presented. The microengine provides output in the form of a continuously rotating output gear (50 μm in diameter) that is capable of delivering torque to additional geared mechanisms. The microengine can be operated at varying speeds and its motion can be reversed. A rotational speed of up to 200000 r/min while driving multiple gears has been obtained. Drive of a 1600 μm diameter optical shutter has also been demonstrated. The resultant microengine and gear train, produced by polysilicon surface-micromachining techniques, are completely batch-fabricated without the need for piece-part assembly     

A sublithographic antifuse structure for field-programmable gatearray applications

The authors demonstrate an antifuse structure with a cell area of 0.2×0.2 μm² which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2-μm lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse     

3.5-mm-square InGaAs p-i-n photodiodes and their application tooptical-axis arrangement between 1.3-μm laser diodes and a SMF

InGaAs p-i-n photodiodes (PD) with 3.5-mm×3.5-mm-large photosensitive area have been fabricated using chlorine-vapor-phase-epitaxial (C-VPE) growth. They showed high responsivity of 0.95 A/W (λ=1.3 μm) and 1.2 A/W (λ=1.55 μm) and good homogeneity in the whole area. Long-term reliability was confirmed through high-temperature aging tests at 150°C up to 5200 hours. A PD with two pairs of parallel electrodes (PE-PD) was applied to optical-axis arrangement between 1.3-μm laser diodes (LD's) and a single mode fibre (SMF). The beam position of a LD was detected in error within ±20 μm using PE-PD prior to coupling of a LD beam into a SMF. Total inspection time was reduced to one third the original time     

LD optical switch with polarization insensitivity over a widewavelength range

A double-heterostructure (DH) laser with TM mode lasing has been achieved with a narrow active-layer width, and a laser-diode optical switch (LDSW) module with less than a 0.35-dB gain difference between the TE and TM modes over a wide wavelength range has been constructed by introducing a square bulk active layer formed by dry etching and regrowth. The polarization-insensitive width of a 0.3-μm-thick DH laser is clarified to be between 0.30 and 0.35 μm, since the 0.30- and 0.35-μm-wide DH lasers lase in the TM mode and TE mode, respectively. The polarization-insensitive width of the fabricated 0.3-μm-thick LDSW is estimated to be about 0.32 μm for the fabricated LDSW with a trapezoidal active layer by measuring the single-pass gain and the gain difference between the TE and TM modes. This must be to within 0.01 μm. A 0.35-μm-wide, 300-μm-long LDSW module has lossless gain in the wavelength range of 1.31 to 1.36 μm at 20 mA. The gain difference between the TE and TM modes is as low as 0.35 dB, The rise and fall times are 1.0 and 0.55 ns, respectively. The bulk active-layer LDSW module is promising for use as a polarization-insensitive optical-gate switch in optical information systems     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

Optical WDM transceiver module using wavelength-selective couplerand WDM-PD for optical access networks

A new optical wavelet division multiplexing (WDM)-transceiver module has been designed and fabricated for optical access networks. Conventional 1.3/1.55-μm WDM-coupler and Y-branch were replaced by a new wavelength-selective coupler in order to reduce module size. A new WDM-photodiode (PD), which was photosensitive to 1.3 μm light and transparent to 1.55 μm light, and a 1.55-μm PD were arranged in series along the optical axis. An MQW-FP-LD was used as a 1.3-μm transmitter. Fundamental characteristics were measured and discussed. Evaluation results, P_out of 0 dBm, responsivity of 0.36 A/W at 1.31 μm and 0.74 A/W at 1.55 μm, and IMD2 of -76.2 dBc, imply that this WDM-transceiver module design is promising to application for optical access networks     

1.55-μm InGaAsP-InP spot-size-converted (SSC) laser with simpletechnological process

In this letter, we report the realization of a 1.55-μm spot-size-converted (SSC) laser using conventional SCH-MQW active layers and conventional photolithography. The laser consists of a 300-μm-long rectangular gain section, with compensated multiple-quantum-well (MQW) structure, and a 300-μm-long tapered passive waveguide, fabricated on lower SCH layer. The device exhibits a beam divergence of 13°×18° and 3.5-dB coupling loss with a cleaved single-mode fiber (SMF). The 1-dB alignment tolerance is ±2.3 μm in the vertical direction and ±1.9 μm in the lateral direction, respectively     

Low resistance intracavity-contacted oxide-aperture VCSELs

The authors study, analytically and experimentally, the extrinsic series resistance in intracavity-contacted vertical-cavity surface-emitting lasers (VCSEL's). Low resistance, low threshold-current, intracavity-contacted VCSELs are fabricated, with resistances ranging from 355 Ω for 4-μm square apertures to 80 Ω for 12-μm square apertures and threshold voltages as low as 1.35 V. To the best of our knowledge, these are the lowest values reported for this type of VCSEL. The threshold currents range from 270 μA for 4 μm×4 μm apertures to 850 μA for 12 ×12 μm. From a comparison of the resistance as a function of oxide aperture radius, the measured data follows closely with the calculated data, demonstrating the validity of the derived expressions for series resistance     

A 50-MHz 8-Mbit video RAM with a column direction drive senseamplifier

An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm², and the chip area is 12.7×16.91 mm²     

A high gain n-well/gate tied PMOSFET image sensor fabricated from astandard CMOS process

The performance of a high gain photodetector fabricated using a standard 0.8-μm, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular to the current flow. The n-well potential modulated by illumination is fed back to the gate through the well-to-gate connection, which results in an extra current amplification beyond that of a normal PMOSFET biased in the lateral bipolar mode. A high responsivity of 2.5×10³ A/W has been measured with an operating voltage as low as 0.3 V for a W/L of 8.2 μm/0.8 μm. The impact of technology scaling on the performance of the photodetector are also studied. A simple 32×32-pixel image sensor array was fabricated to demonstrate the feasibility of integrating the new device in actual circuit applications     

A floating-gate MOSFET with tunneling injector fabricated using astandard double-polysilicon CMOS process

A floating-gate MOSFET which is programmable in both directions by Fowler-Nordheim tunneling and is fabricated using an inexpensive standard 2-μm double-polysilicon CMOS technology is discussed. Tunneling occurs at a crossover of polysilicon 1 with polysilicon 2. Device layout and basic device characteristics are presented, and recommendations for efficient programming are given. This is the first floating-gate FET with a tunneling injector fabricated in standard technology that has close to symmetric programming characteristics for both charging and discharging of the gate     

Threshold currents of 1.3-μm bulk, 1.55-μm bulk, and1.55-μm MQW DFB P-substrate partially inverted buried heterostructurelaser diodes

We investigate the threshold currents of 1.3-μm bulk, 1.55-μm bulk, and 1.55-μm multi-quantum-well (MQW) distributed feedback (DFB) P-substrate partially inverted buried heterostructure (BH) laser diodes experimentally and theoretically. In spite of the larger internal loss of the 1.55-μm bulk laser diodes, the threshold current of the 1.55-μm bulk DFB P-substrate partially inverted BH laser diode is almost the same as that of the 1.3-μm bulk DFB P-substrate partially inverted BH laser diode. The experimentally obtained average threshold current of the 1.3-μm bulk DFB P-substrate partially inverted BH laser diodes is 17 mA and that of the 1.55 μm bulk DFB P-substrate partially inverted BH laser diodes is 16 mA. The calculated threshold current of the 1.3-μm bulk DFB laser diode is 15.3 mA and that of the 1.55-μm bulk DFB laser diode is 18.3 mA, which nearly agree with the calculated values, respectively. We have fabricated two types of five-well 1.55-μm InGaAs-InGaAsP MQW DFB P-substrate partially inverted BH laser diodes. One has barriers whose bandgap energy corresponds to 1.3 μm, and the other has barriers of which bandgap energy corresponds to 1.15 μm. The calculated threshold current of the MQW DFB laser diode with the barriers (λ_g =1.3 μm) is 8.5 mA, which nearly agrees with the experimentally obtained value of 10 mA. However, the calculated threshold current of the MQW DFB laser diode with the barriers (λ_g=1.15 μm) is 7.9 mA which greatly disagrees with the experimentally obtained value of 19 mA, which suggests that the valence band discontinuity between the well and the barrier severely prevents the uniform distribution of the injected holes among five wells     

A pixellated grating array using photoelectrochemical etching on aGaAs waveguide

We have demonstrated and evaluated a grating array outcoupler fabricated by photoelectrochemical (PEC) etching, a manufacturable and practical approach for fabrication of grating-based III-V semiconductor waveguide devices. An array of submicron period gratings was etched into photolithographically delineated areas in a single PEC step. The fabricated devices are: 10-μm wide rib waveguides with 0.35-μm first-order outcoupling gratings; and 10-μm wide rib waveguides with 10 μm×10 μm pixellated areas of gratings. Device characterization demonstrates the effectiveness of outcoupling grating fabrication using PEC and that the pixellated grating outcoupler is an effective and simple means of generating an optical beam array     

Measurements of a fabricated micro mirror using a lateral-effectposition-sensitive photodiode

The characteristics of a fabricated micro mirror were determined using an optical measurement system. The system consisted of a helium-neon laser, a p-i-n lateral-effect photodiode, and other fundamental optical elements. For testing, we used a micro mirror array (1×4) in which each mirror was composed of a mirror plate, two torsional flexure hinges, two address electrodes, and two support posts. A mirror plate was designed to a size of 100×110×1.5 μm ³ and the hinge size was 20 μm long, 5 μm wide, and 0.5 μm thick. The micro mirror array was fabricated using micromachining technology and a lithography-galvanoformung-abformung-like process using nickel electroplating. The variation in the mirror's deflection angle with applied voltage was measured as a static characteristic. The downward threshold voltage of the 0.5-μm thick hinge was 48 V. The step response time, as a dynamic characteristic, was 21.8 μs when a 64 V step voltage higher than the downward threshold voltage was applied to an address electrode. The lifetime of the fabricated micro mirror was tested for both unidirectional and bidirectional operation     

High-power GaInAsSb-AlGaAsSb multiple-quantum-well diode lasersemitting at 1.9 μm

High-power diode lasers emitting at ~1.9 μm have been fabricated from a quantum-well heterostructure having an active region consisting of five GaInAsSb wells and six AlGaAsSb barriers. For devices 300 μm wide and 1000 μm long, single-ended output power as high as 1.3 W cw has been obtained with an initial differential quantum efficiency of 47%. The pulsed threshold current density is as low as 143 A/cm² for 2000-μm-long devices     

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0-μm-thick films have been fabricated on SOS films 0.2 μm thick that have been grown at growth rates above 4 μm/min     

A 30-ns cycle time 4-Mb mask ROM

A 4-Mb mask ROM in a 256-Kb×16 organization is described. It is fabricated with a 1.0-μm CMOS process, using single polysilicon, two levels of metal, and 3.0×4.4 μm² X-cells. Unlike conventional ROM's, it implements a DRAM type RAS/CAS control scheme. A RAS access time of 60 ns is measured. For a fast data access, the chip has a consecutive address read mode in which the system needs to supply only a first address and subsequent addresses are generated in the ROM chip at every CAS clock. A 30-ns cycle time is demonstrated in this mode. 16-b data pins are also used for RAS/CAS multiplexed address inputs. Because of this three way pin multiplexing, the 7.5×10.5 mm² chip needs only 28 pins for its 400-mil SOJ package     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance