Thermal feedback in power semiconductor devices

Thermal feedback (TF) is an important aspect for the thermal management of semiconductor devices and high-power density integrated circuits. Different features of positive and negative TF in transistors are reviewed and summarized for the macroscopic domain. The thermal feedback mechanism is applied to the microscopic domain of noise fluctuations in semiconductor devices. It is argued that TF may be responsible for a major part of 1/fflicker or excess noise. Some experimental evidence is presented which supports this thermal feedback 1/f-noise theory for bipolar and MOS field effect transistors. Device and circuit design rules for the minimization of transmitter noise are given.     

Trends in power semiconductor devices

This paper reviews recent trends in power semiconductor device technology that are leading to improvements in power losses for power electronic systems. In the case of low voltage (<100 V) power rectifiers, the silicon P-i-N rectifier has been displaced by the silicon Schottky rectifier, and it is projected that the silicon TMBS rectifier will be the preferred choice in the future. In the case of high voltage (>100 V) power rectifiers, the silicon P-i-N rectifier continues to dominate but significant improvements are expected by the introduction of the silicon MPS rectifier followed by the GaAs and SiC based Schottky rectifiers. Equally important developments are occurring in power switch technology. The silicon bipolar power transistor has been displaced by silicon power MOSFETs in low voltage (<100 V) systems and by the silicon IGBTs in high voltage (>100 V) systems. The process technology for these MOS-gated devices has shifted from V-MOS in the early 1970s to DMOS in the 1980s, with more recent introduction of the UMOS technology in the 1990s. For the very high power systems, the thyristor and GTO continue to dominate, but significant effort is underway to develop MOS-gated thyristors (MCTs, ESTs, DG-BRTs) to replace them before the turn of the century. Beyond that time frame, it is projected that silicon carbide based switches will begin to displace these silicon devices     

Hot rocks [single crystal diamond for power semiconductor devices]

This article describes the production, using chemical vapour deposition, of single crystal synthetic diamonds. It then discusses their practical use in semiconductor devices. Diamond is a wide band gap semiconductor with high breakdown voltage, high saturation velocity, high carrier mobility, and high thermal conductivity. In addition it is extremely radiation hard. Diamond semiconductors are ideal for high-power, high-frequency electronic applications.     

Rigorous modeling of high-speed semiconductor devices

We present a review of industrial heterostructure devices based on SiGe/Si and III–V compound semiconductors analyzed by means of numerical simulation. A comparison of device simulators and current transport models is given and critical modeling issues are addressed. Results from two-dimensional hydrodynamic analyses of heterojunction bipolar transistors (HBTs) are presented in good agreement with measured data. The examples are chosen to demonstrate technologically relevant issues which can be addressed by device simulation.     

Numerical modeling of magnetic-field-sensitive semiconductor devices

Semiconductor devices in the presence of a magnetic field have been modeled numerically. The two-dimensional distributions of the electric potential, the electron concentration, and the hole concentration in a silicon slab exposed to a magnetic field have been computed. We have generalized the well-known Scharfetter-Gummel scheme to the case of two dimensions and nonzero magnetic field and employed a finite-difference technique. Our results are in support of earlier results in case of Hall plates. In intrinsic or closely intrinsic silicon, our results show both magnetoconcentration and space-charge effects. As a realistic example of a magnetic-field sensor, we have modeled a p⁺-i-n⁺silicon diode with split contacts.     

Electrostatic discharge thermal failure in semiconductor devices

The problem of calculating for electrostatic discharge (ESD) thermal failure is considered by the thermal convolution integral technique. It is shown that the common assumption that threshold failure occurs after five time constants is unjustified and that the simple average power method for assessing threshold parameters is, consequently, invalid. New expressions for the threshold parameters are presented which retain the simplicity of the average power method, yet represent only a small sacrifice of the accuracy (typically 5%) of more complex methods. In addition, the relaxation of the constraints of a pure Wunsch-Bell damage profile and of an exponentially decaying current pulse is considered     

Studies of turn-off effects in power semiconductor devices

An analytical model has been developed for analyzing current and voltage transients during high power diode recovery. Using the charge control approach and approximating the excess charge distribution by simple geometrical curves a fast and convenient method for computer analysis is obtained. The model is thoroughly physical and makes use of the proper diode design parameters and the differential equations of the electrical network. There is no need for any experimental fitting parameter. All relevant complicating effects as emitter recombination, nonabrupt pn-junction and reverse current influence on the space-charge layer are considered. Comparisons between calculated and measured recovery behavior under several different conditions show good agreement and prove that the model may serve as a useful tool in device and circuit development including RC-snubber design. Furthermore, the calculated charge distribution varies during the recovery in a physically reasonable manner. Starting from measured recovery transients this model may also be used as a new method for determining the excess charge content in the diode at the beginning of the recovery phase.     

功率半导体器件的发展和市场

功率半导体器件的全球销售额每年以约１５％的速率增长,而传统器件如ＳＣＲ和ＧＴＲ等的年增长率远小于新型器件。以Ｓｍａｒｔ Ｐｏｗｅｒ为代表的新型功率器件集功率、控制和信息于一体,是今后发展的重点。     

Doping of semiconductor devices by Laser Thermal Annealing

In today's highly competitive semiconductor industry, and due to the accelerating pace of technology development, the integration of new and disruptive solutions to address process limitations is a mandatory requirement, although most challenging, Doping, i.e. the ability to control material properties locally and by extension local strain engineering, are amongst the key process variables used to overcome device performance issues. With the emergence of three-dimensional (3D) devices and architectures at the nanoscale, new doping schemes which rely on low thermal budgets are being evaluated, especially in the framework of new materials introduction such as germanium (Ge) and III-Vs in front end logic, defect engineered oxides and phase change materials in memory, or silicon carbide (SiC) and gallium nitride (GaN) in power devices.Ultrafast sub-µs annealing schemes with shallow penetration depths providing localized impact, such as Laser Thermal Anneal (LTA), are some of the most promising and scalable approaches being evaluated today. Its production worthiness is already established as process of record for high volume manufacturing of several 3D stacked architectures such as vertical silicon (Si) and SiC power devices and complementary-metal-oxide-semiconductor (CMOS) imaging sensors.This paper reviews recent work highlighting the potential of LTA as an enabler for next generation technologies covering a wide range of applications from Logic to Nano-Electro-Mechanical Systems (NEMS) and 3D sequential integration.     

面向开关过程的大功率电力电子器件建模

传统的大功率电力电子装置仿真中,通常将电力电子装置的开关动态过程视为理想过程,不能如实反映工作过程中的电压电流尖峰脉冲对系统的影响,针对该问题文章提出了一种面向开关过程的大功率电力电子器件建模方法,运用插值建模的方法,对大功率电力电子器件进行兼顾全面性和细致性的仿真,正确反映开关动态过程中大功率电力电子器件过程中的电压电流尖峰现象,从而获得较高的仿真精度。     

Thermal resistance assessment in multi-trenched power devices

For the first time the thermal resistance (R_th) of Multi-Trenched (MT) power devices is evaluated and compared with their Deep Trench Isolation flanked (DTI-flanked) and bulk counterparts. The R_th extraction is carried out by adapted test structures based on the four-point heater/sensor method. Additional TCAD simulation supports the experimental stationary values and proves that dynamic heating can limit the MT power devices energy capability.     

Cosmic ray induced failures in high power semiconductor devices

Recently it was discovered that cosmic rays can induce failures in large area, high voltage power semiconductors. The effect is of considerable practical significance and has caused a series of equipment malfunctions in the field. We show that earlier attempts to model the physical process of failure are inadequate and introduce a new model. From the new model we derive a phenomenological law for the failure rate as a function of simple design parameters. The law has only two adjustable parameters and the parameters have a simple physical interpretation. In particular the parameter which describes the slope of the extrapolation curve from test to field conditions can be calculated from first principles and shows good agreement with the experimentally found value. This gives high confidence in the validity of the extrapolation law. We give mathematical expressions and diagrams to quantify the safe operating conditions with respect to the cosmic ray failure mode for all high voltage power devices. This allows the user to design reliable power electronic equipment and the semiconductor manufacturer to design devices virtually immune against this failure mode.     

Electromigration failure modes in aluminum metallization for semiconductor devices

Two wear-out type failure modes involving aluminum metallization for semiconductor devices are described. Both modes involve mass transport by momentum exchange between conducting electrons and metal ions. The first failure mode is the formation of an electrically open circuit due to the condensation of vacancies in the aluminum to form voids. The second is the formation of etch pits into silicon by the dissolution of silicon into aluminum, and the transport of the solute ions down the aluminum conductor away from the silicon-aluminum interface by electron wind forces. The process continues until an etch pit grows into the silicon to a depth sufficient to short out an underlying junction.     

Annealing effects of NTD silicon for semiconductor power devices

The use of neutron transmutation doped (NTD) Si has become very important for processing high-voltage power devices. A simple annealing process is usually required to anneal the lattice defects caused by neutron irradiation. This is usually performed by the silicon supplier by annealing the silicon crystal at a low temperature (approximately 700°C). High-voltage power devices, however, require much higher processing diffusion temperature. In situ annealing of silicon, therefore, can occur during device processing. Furthermore, we demonstrate here that higher yield can be obtained using the in situ annealing. This improvement is due to the effectiveness and uniformity of annealing of thin wafers. The uniformity and blocking voltage distribution of high-voltage rectifiers and thyristors using crystal annealed and in situ wafer annealed NTD silicon are presented.     

Performance comparison of wide bandgap semiconductor rf power devices

Impressive radio frequency power performance has been demonstrated by three radically different wide bandgap semiconductor power devices, SiC metal semiconductor field effect transistors (MESFETs), SiC static induction transistors (SITs), and AlGaN heterojunction field effect transistors (HFETs). AlGaN HFETs have achieved the highest f_max of 97 GHz. 4H-SiC MESFETs have achieved the highest power densities, 3.3 W/mm at 850 MHz (CW) and at 10 GHz (pulsed). 4H-SiC SITs have achieved the highest output power, 450 W (pulsed) at 600 MHz and 38 W (pulsed) at 3 GHz. Moreover, a one kilowatt, 600 MHz SiC power module containing four multi-cell SITs with a total source periphery of 94.5 cm has been demonstrated.