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通过引入缓冲层可以提高器件的二次击穿电压,进而提高器件发生单粒子烧毁的阈值电压。本文提出采用线性掺杂缓冲层结构。通过准静态雪崩仿真和重离子入射仿真发现,优化线性缓冲层是必要的,对于固定厚度的缓冲层,具有线性掺杂缓冲层结构的器件发生单粒子烧毁时的内部电场强度明显小于优化后的恒定掺杂缓冲层结构的器件。二次击穿电压与寄生晶体管的开启电流明显比具有优化后的恒定掺杂缓冲层结构的器件高。因此,线性掺杂缓冲层结构的器件在抗单粒子烧毁方面更有优势。  相似文献   

3.
Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application.Single event gate rupture (SEGR) and single event burnout (SEB),which will degrade the running safety and reliability of spacecraft,are the two typical failure modes in power MOSFETs.In this paper,based on recombination mechanism of interface between oxide and silicon,a novel hardened power MOSFETs structure for SEGR and SEB is proposed.The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers.Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV.cm2/mg in the whole incident track,and the other parameters are almost maintained at the same value.Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.  相似文献   

4.
功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明:对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。  相似文献   

5.
功率VDMOS器件是航天器电源系统配套的核心元器件之一,在重粒子辐射下会发生单粒子烧毁(SEB)和单粒子栅穿(SEGR)效应,严重影响航天器的在轨安全运行。本文在深入分析其单粒子损伤机制及微观过程的基础上,发现了功率VDMOS器件在重粒子辐射下存在SEBIGR效应,并在TCAD软件和181Ta粒子辐射试验中进行了验证。引起该效应的物理机制是,重粒子触发寄生三极管,产生瞬时大电流,使得硅晶格温度升高,高温引起栅介质层本征击穿电压降低,继而触发SEGR效应。SEBIGR效应的发现为深入分析功率MOSFET器件的单粒子辐射效应奠定了理论基础。  相似文献   

6.
阐述了空间辐射环境下n沟功率VDMOSFET发生单粒子栅穿(SEGR)和单粒子烧毁(SEB)的物理机理。研究了多层缓冲局部屏蔽抗单粒子辐射的功率VDMOSFET新结构及相应硅栅制作新工艺。通过对所研制的漏源击穿电压分别为65V和112V两种n沟功率VDMOS-FET器件样品进行锎源252Cf单粒子模拟辐射实验,研究了新技术VDMOSFET的单粒子辐射敏感性。实验结果表明,两种器件样品在锎源单粒子模拟辐射实验中的漏源安全电压分别达到61V和110V,验证了新结构和新工艺在提高功率VDMOSFET抗单粒子效应方面的有效性。  相似文献   

7.
Simulating single-event burnout of n-channel power MOSFET's   总被引:2,自引:0,他引:2  
Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs  相似文献   

8.
With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32 nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure. Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.  相似文献   

9.
基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(UGS=3 V,UDS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(UGS=0 V,UDS=300 V)和零压偏置(UGS=UDS=0...  相似文献   

10.
构建了一个半径为0.05μm的圆柱体,用于模拟单粒子辐射功率VDMOS器件的粒子径迹,且圆柱体内新生电子和新生空穴的数目沿圆柱体的半径方向呈高斯分布。考虑到功率VDMOS器件的SEB效应与寄生NPN具有直接关系,提出了一种畸变NPN模型,并通过合理假设,推导出功率VDMOS器件在单粒子辐射下安全漏源偏置电压的解析式。结果表明,使用解析式计算得到的SEB阈值与TCAD仿真结果吻合较好。该模型可被广泛用于功率VDMOS器件SEB效应的分析和评价,为抗辐射功率VDMOS器件的选型及评价提供了一种简单和廉价的方法。  相似文献   

11.
Undoped AlGaN/GaN HEMTs for microwave power amplification   总被引:5,自引:0,他引:5  
Undoped AlGaN/GaN structures are used to fabricate high electron mobility transistors (HEMTs). Using the strong spontaneous and piezoelectric polarization inherent in this crystal structure a two-dimensional electron gas (2DEG) is induced. Three-dimensional (3-D) nonlinear thermal simulations are made to determine the temperature rise from heat dissipation in various geometries. Epitaxial growth by MBE and OMVPE are described, reaching electron mobilities of 1500 and 1700 cm 2/Ns, respectively, For electron sheet density near 1×1013/cm2, Device fabrication is described, including surface passivation used to sharply reduce the problematic current slump (dc to rf dispersion) in these HEMTs. The frequency response, reaching an intrinsic ft of 106 GHz for 0.15 μm gates, and drain-source breakdown voltage dependence on gate length are presented. Small periphery devices on sapphire substrates have normalized microwave output power of ~4 W/mm, while large periphery devices have ~2 W/mm, both thermally limited. Performance, without and with Si3N4 passivation are presented. On SiC substrates, large periphery devices have electrical limits of 4 W/mm, due in part to the limited development of the substrates  相似文献   

12.
A simple rate-equation-based thermal VCSEL model   总被引:3,自引:0,他引:3  
Motivated by the potentially large number of devices and simulations involved in optoelectronic system design, and the associated need for compact optoelectronic device models, we present a simple thermal model of vertical-cavity surface-emitting laser (VCSEL) light-current (LI) characteristics based on the laser rate equations and a thermal offset current. The model was implemented in conventional SPICE-like circuit simulators, including HSPICE, and used to simulate key features of VCSEL LI curves, namely, thermally dependent threshold current and output-power roll-over for a range of ambient temperatures. The use of the rate equations also allows simulation in other non-dc operating regimes. Our results compare favorably to experimental data from three devices reported in the literature  相似文献   

13.
The latest low-profile high-power inductors, used in DC-DC converters to power an assortment of applications, are going endlessly smaller and submitted to larger amount of current.This surface-mounted magnetic component is commonly constructed using a wound copper coil which is over-moulded in a Soft Magnetic Composite (SMC) based on an iron-resin material mixture.The performances of that high-power density device depend closely on the coupled interaction of magnetic phenomenon, joule effect and thermal behaviour, which is difficult to apprehend at board level simulation. Thus, the present study highlights the electromagnetic phenomena encountered by SMC inductor devices and their influence on the temperatures of the iron-based core and copper-based coil.In order to better characterize the behaviour of high-power inductor devices, a set of coupled electromagnetic and thermal simulations were performed on the case of an industrial demonstration electronic board. Consequently, the influence of surrounding active electronic components upon the acceptable temperature rise of the inductor parts has been investigated.The numerical simulations were completed by electrical characterizations and thermal measurements on the test vehicle for various operating conditions with the purpose to establish a more realistic thermal model of the inductor device.The agreement of the fine detailed model with experiment results is quite relevant: the divergence is lower than 10%.Further, for minimizing the expensive meshing of the finely detailed simulations and the computation time, a novel concept of compact thermal model for inductor device, based on DELPHI methodology, was used. The deducted two-heating-source DELPHI-style model adequately correlates the physical behaviour of all heat paths of the inductor device, our purpose.  相似文献   

14.
In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔTj) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔTj and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.  相似文献   

15.
It is essential in the simulation of power electronics applications to model magnetic components accurately. In addition to modeling the nonlinear hysteresis behavior, eddy currents and winding losses must be included to provide a realistic model. In practice the losses in magnetic components give rise to significant temperature increases which can lead to major changes in the component behavior. In this paper a model of magnetic components is presented which integrates a nonlinear model of hysteresis, electro-magnetic windings and thermal behavior in a single model for use in circuit simulation of power electronics systems. Measurements and simulations are presented which demonstrate the accuracy of the approach for the electrical, magnetic and thermal domains across a variety of operating conditions, including static thermal conditions and dynamic self heating  相似文献   

16.
利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1 200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。  相似文献   

17.
By combining low-cost printed circuit board technology and focused ion beam techniques, a simple method has been developed to produce thermal microsensors in a robust package with straightforward electrical connectivity. Two devices have been developed to demonstrate the principle. The first was fabricated using a single step process comprised of FIB deposited platinum. The second device utilised a multistep process using FIB milled thermally evaporated Au on a PCB platform with through-plated vias. The performance of these devices was tested by measuring their thermo-electrical characteristics.  相似文献   

18.
A finite element model was developed to simulate the temperature distributions produced by radiofrequency catheter ablation. This model incorporated blood, myocardium and torso tissues. The Laplace equation was solved to determine the steady-state electric field. The heat generation in the tissues was then computed from the power density distribution and the bioheat equation was solved to determine the time-varying temperature distribution, taking into account the convective energy exchange at the blood-myocardium and torso-air interfaces. This model was used to predict the lesion depth and to evaluate the effects of electrode location, changes of the electrical and thermal conductivities, and the electrode radius on the thermally induced damage to the myocardium. Temperature distributions induced by radiofrequency ablation were found to be: i) not very sensitive to the reference electrode location, ii) more sensitive to electrical conductivity changes than to thermal conductivity changes, and iii) larger electrodes allow a current distribution at higher level of power with reducing the chance of impedance rise  相似文献   

19.
The idea of including non-uniform temperature distribution into power semiconductor device models is not new, as accurate electro-thermal simulations are required for designing compact power electronic systems (as integrated circuits or multi-chip modules). Electro-thermal simulations of a PIN-diode based on the finite-element method, show a non-uniform temperature distribution inside the device during switching transients. Hence the implicit assumption of a uniform temperature distribution when coupling an analytical electrical model and a thermal model yields inaccurate electro-thermal behaviour of the PIN-diode so far. If literature reports procedures regarding complex thermal network modelling, few papers address the problem of mixing adequately electrical and thermal issues. Instead of using a one-dimensional finite difference or element method, the bond graphs and the hydrodynamic method are used to build a 1D electro-thermal model of the PIN-diode. The paper focuses on electrical issues and the proper expression and localization of power losses to feed the thermal network model. The results by this original technique are compared with those given by a commercial finite-element simulator. The results are similar but the computation effort attached to the proposed technique is a fraction of that required by finite-element simulators. Moreover the proposed technique may be applied easily to other power semiconductor devices.  相似文献   

20.
Even though low voltage MOSFETs are fairly intrinsically robust to SEB, the high current pulses that arise in certain charge generating mechanisms may lead to circuit malfunction. In this work, for the first time, the current pulses induced by ion impacts in new generation commercial power MOSFETs are characterized by a statistical analysis. This approach allows us to evidence the existence, in these devices, of two different charge generation mechanisms. Furthermore, the capability to easily quantify these phenomena provides useful information for the design of circuits using these MOSFETs. The pulse shape and the total charge generated by the impact of an energetic ion are studied in relation to the energy and species of the ion and the applied voltage between drain and source.  相似文献   

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