H.264视频解码器中帧内预测模块的硬件设计

提出一种能实时处理的H.264/AVC帧内预测硬件结构.通过对H.264/AVC各个预测模式的分析,设计了一个通用运算单元,提高了硬件资源的可重用性.采用4个并行运算单元计算预测值,对运算比较复杂的plane模式预处理,并设计模式预测器,加快了系统处理速度.硬件电路结构已通过RTL级仿真及综合,并在Altera公司的C...     

基于多尺寸特征融合的快速转码算法

为了降低H.264转码器的运算复杂度,满足视频转码实时应用的要求,提出一种结合多尺寸视频特征的快速视频转码帧内预测算法。首先利用二维直方图提取小尺寸视频中宏块的空间特性,结合双阈值的方法,选择Intra 16×16或Intra 4×4模式。然后从输入的视频码流中提取编码信息组成多维特征向量训练支持向量机(SVM)分类器模型,通过SVM建立大尺寸视频编码信息与小尺寸视频宏块编码模式之间的联系,进而对Intra 4×4中的9种模式进行细分。此算法减少了预测模式数量,实现率失真优化算法的提前终止,在高效转码的同时保证了转码后视频的高质量。     

H．264帧内方向预测的研究

在H．264视频编解码标准中,帧内4×4亮度块的预测模式有9种。在对这些预测模式的预测能力进行分析后．发现在不同帧内预测模式预测能力存在差异。为了解决这一问题,提出了一种更改编解码次序的方法对预测能力较差的模式进行编解码。实验结果表明该方法可以使预测能力较差的模式的预测能力得到改善．     

基于FPGA的AVS编码器帧内预测实现

针对帧内预测的快速算法,由于DSP架构软件顺序执行的局限性难以满足实时性要求,而FPGA以其高速的计算速度和强大的并行处理能力成为H.264和AVS编解码的理想平台。本文在FPGA平台上采用资源共享、高并行和多流水线结构实现了亮度帧内预测算法。该方法在分析AVS帧内亮度5种预测模式的基础上,将像素预测与模式判决在一个模块中完成,并且利用各模式预测的相似性,实现运算单元共享和多种模式并行执行,兼顾了处理速度和实现代价。仿真及综合结果表明该设计能够完全满足标清(704×576,30f/s)数字视频的实时处理要求。     

H.264/AVC快速帧内预测算法的研究

H.264/AVC采用先进的帧内预测技术,进一步提高了编码效率,但计算复杂度也随之增高。提出了一种快速的帧内预测算法。该算法充分利用宏块的MAD信息及时间/空间相关性,对宏块进行预判,在帧内4×4（I4）和帧内16×16（I16）预测模式之间进行选择;然后,针对I4预测,计算当前块与参考块之间的相似程度D(b_x,b_r),据此判断是否跳过当前块的模式选择过程,从而减少了编码时间。实验表明,与JM10.2相比,针对全I帧测试：编码时间平均减少约59.03%;针对IPPP测试：编码时间平均减少22.76%;SNRY和码率基本不变。并且,该算法有利于在硬件平台(FPGA)上实现,可用于实际的视频通信产品。     

Hybrid linear weighted prediction and intra block copy based light field image coding

Light field imaging can capture both spatial and angular information of a 3D scene and is considered as a prospective acquisition and display solution to supply a more natural and fatigue-free 3D visualization. However, one problem that occupies an important position to deal with the light field data is the sheer size of data volume. In this context, efficient coding schemes for this particular type of image are needed. In this paper, we propose a hybrid linear weighted prediction and intra block copy based light field image codec architecture based on high efficiency video coding screen content coding extensions (HEVC SCC) standard to effectively compress the light field image data. In order to improve the prediction accuracy, a linear weighted prediction method is integrated into HEVC SCC standard, where a locally correction weighted based method is used to derive the weight coefficient vector. However, for the non-homogenous texture area, a best match in linear weighted prediction method does not necessarily lead to a good prediction of the coding block. In order to alleviate such shortcoming, the proposed hybrid codec architecture explores the idea of using the intra block copy scheme to find the best prediction of the coding block based on rate-distortion optimization. For the reason that the used “try all then select best” intra mode decision method is time-consuming, we further propose a fast mode decision scheme for the hybrid codec architecture to reduce the computation complexity. Experimental results demonstrate the advantage of the proposed hybrid codec architecture in terms of different quality metrics as well as the visual quality of views rendered from decompressed light field content, compared to the HEVC intra-prediction method and several other prediction methods in this field.     

基于方向测度的H.264快速帧内预测算法

H.264在空间域上从多个方向进行多种模式的帧内预测,并使用率失真优化算法选择最佳模式,使编码的复杂度大幅增加。为此,提出了一种基于方向测度的快速帧内预测算法。该算法使用方向测度来判断块的平坦程度和纹理方向,它可以预先排除可能性小的预测模式,避免了不必要的代价计算。实验结果表明,算法在保持信噪比平均降低0.05 dB和码率平均增加1.27%基础上,编码时间平均减少了39.16%。     

一种H.264帧内预测模式的快速选择算法

H.264/AVC视频编码标准采用码率—失真度最优化(RDO)算法,以保证更高的压缩效率和更好的图像质量,但同时也大大增加了编码器的复杂度和运算负担。本文提出了一种新型的帧内预测模式的快速选择算法,该算法基于图像内部信息的变化剧烈程度进行判断,并通过方向矢量来减少候选帧内预测模式。试验结果表明,该算法可以将整个编码时间减少到原来采用RDO算法时的40%~50%,而且和RDO算法比较,最终压缩后的视频图像质量基本没有下降。     

基于FPGA的H.264帧内预测实现和优化

在使用硬件电路进行H.264编码时,为提高帧内预测运算速度,减少硬件电路面积,提出一种基于现场可编程门阵列(FPGA)的H.264帧内预测硬件电路的实现和优化解决方案。利用FPGA的并行处理能力和同模式下帧内预测数据冗余对硬件电路进行优化。使用Verilog语言进行模块设计,仿真平台为Modelsim,在Altera CycloneII EP2C20F484C上的实现,验证了该硬件电路结构的高效性及实用性。     

H.264帧内4×4块预测模式选择快速算法研究

在H．264视频编码过程中，编码时间受诸多因素的影响，如帧间／帧内模式选择、运动估计（ME）、率失真优化（RDO）等。为了以较快速度和较好质量进行编码，针对H．264帧内模式选择，提出了一种适用于H．264帧内4×4块预测的模式选择快速算法。该算法利用帧内4×4块最优预测模式与和它相邻的预测模式之间率失真代价（RDCost）的高相关性，以及绝对变换误差和（SATD）与率失真（RD）性能之间的强相关性，有效地跳过一些不太可能的预测模式，从而使帧内4×4块模式选择过程只需进行4次率失真代价计算即可。实验结果显示，该算法在编码性能和编码速度之间取得了很好的折衷。     

An AR based fast mode decision for H.265/HEVC intra coding

As a critical technique to raise coding efficiency in H.265/HEVC (H.265/High Efficiency Video Coding), the number of prediction modes for intra coding is much larger than that in H.264/AVC. However, the large number of prediction modes also leads to high complexity. In this paper, an AR (Auto Regression) based fast mode decision method for H.265/HEVC intra coding is proposed, including an AR based fast mode selection and an MPM (Most Probable Mode) joint fast mode selection method. Considering the correlation between SATD (Sum of Absolute Transformed Differences) cost and RD (Rate-Distortion) cost, we establish a selective function controlled by an adaptive parameter which is acquired by an AR model. According to the distribution of the SATD cost, the selective function can decide which modes can be discarded and which modes can be used for the FMD (Fine Mode Decision). In addition, in order to further reduce the number of candidate modes for FMD, an MPM joint fast mode selection method is presented based on the relationship between MPMs and candidate modes. Experimental results show that just in PU layer, the proposed AR based fast intra mode decision method can save encoding time by 32 % with negligible coding loss in all-intra main configuration compared to the intra mode decision of HM13.0.     

A low energy intra prediction hardware for high efficiency video coding

Intra prediction algorithm in the recently developed high efficiency video coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose pixel equality and pixel similarity based techniques for reducing amount of computations performed by HEVC intra prediction algorithm and, therefore, reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4 × 4 and 8 × 8 luminance angular prediction modes with a small comparison overhead. Pixel equality based technique does not affect the PSNR and bit rate. Pixel similarity based technique increases the PSNR slightly for some video frames and it decreases the PSNR slightly for some video frames. We also designed and implemented a low energy HEVC intra prediction hardware for 4 × 4 and 8 × 8 angular prediction modes including the proposed techniques using Verilog HDL. The proposed techniques significantly reduce the energy consumption of this HEVC intra prediction hardware.     

一种改进的H.264 Intra 4×4帧内预测算法

H.264帧内编码通过空间预测减小变换编码输入值的大小,提高编码压缩性能。由于块编码总按照从左往右和从上往下的顺序,帧内预测可选的参考像素限制于块的左边和上边,因此预测结果不理想。该文提出一种基于宏块内部灵活的子块编码顺序的Intra 4×4预测编码算法,自适应地选择最佳预测参考像素集,同时对空间预测模式进行了改进。通过有限的子块分组和子块顺序选择,可以实现宏块内部编码最优化。仿真试验表明,和H.264相比,该算法可以取得平均0.4 dB 的PSNR编码性能增益。     

HEVC intra coding using vote-based optimization algorithm

We present a voted optimization algorithm utilizing correlation of adjacent frames’ texture feature and thoughts of voted selection for newly proposed video standard High Efficiency Video Coding (HEVC). In addition, a voted algorithm based on original candidate mode collection is developed, which use the candidate modes, to resolve HEVC Most Probable Mode (MPM) mechanism for intra prediction problem. Meanwhile, we perform the vote rules to cut down on candidate collection, which is based on our proposed voted method. Experimental results show that proposed voted algorithm improves the efficiency of encoder by decreasing encoding time with more than 20% and causes nearly negligible increment in bit-rate.     

帧内预测编码的模式抉择与复杂度分级方法

本文提出了一种帧内预测模式抉择方法，利用视频图像的时间相关性和空间相关性，选择部分预测模式对图像块进行帧内预测处理和编码，减少编码的计算复杂度，保持其原有的编码效率。同时提出了一种复杂度分级方法，通过准确控制帧内预测的复杂度，以匹配通信终端有限的计算资源。最后该方法在AVS-M平台中得到了验证。     

一种HEVC帧内预测模式快速选择算法

针对HEVC帧内预测模式选择过程计算较为复杂的问题,提出了一种帧内预测模式快速选择算法。在统计实验数据的基础上,针对64[×]64、32[×]32、16[×]16较大尺寸的预测单元类型,采用阈值法筛选掉粗选后可能性较小的预测模式,针对8[×]8、4[×]4较小尺寸的预测单元类型,根据代价值的分布情况,直接筛减或者采用模式梯度直方图法筛选掉粗选后可能性较小的预测模式,从而减少最后进行率失真代价精密计算的帧内预测模式数量,降低帧内编码复杂度。实验结果表明,在保证图像质量和编码码率的情况下,该算法能有效提高HEVC的编码速度,有利于实时应用。     

Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder

This paper presents a word-level decoding architecture of embedded block coding in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column- switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show that the proposed architecture is capable of decoding 54 MSamples/s at 54 MHz, which can support HDTV 720p (1280 times 720, 4:2:2) decoding at 30 frames/s.     

一种快速的H.264/AVC帧内预测模式选择算法

H.264/AVC采用RDO技术选择帧内和帧间预测模式以进一步提高编码的效率,取得显著效果,但同时大幅度增加了预测的复杂度。该文提出一种RDO模式下的快速Intra_4x4模式选择算法,该算法根据SATD特征以及相邻块的预测模式之间的相关性,可以预先排除约50%可能性小的Intra_4x4模式,避免了不必要的代价(RD_Cost)计算,从而大幅度降低帧内预测的复杂度,同时基本保持了H.264/AVC的编码性能。     

H.264帧内预测快速模式选择

H.264/AVC视频编码标准中用率失真优化(RDO)方法为一个宏块(MB)判决最佳编码模式来提高编码效果,加大了算法复杂度并且计算冗余大。为了克服这一缺点,一种快速帧内预测模式选择算法被提出。在色度预测中,根据宏块的色度纹理复杂度,把原先的4种模式降到1或2种;在亮度16×16块模式判决中,根据最小哈达玛变换的绝对误差和(SATD)来选择最佳模式;在亮度4×4块模式判决中,该算法在9种模式中选择3种可能模式作为候选模式。通过比较16个4×4块总代价与1个16×16块的代价来选择最佳块选择模式,实验表明,该算法能在节省69%左右编码时间的情况下,比特率与峰值信噪比(PSNR)保持不变。     

Fast HEVC I-frame coding based on strength of dominant direction of CUs

High efficiency video coding (HEVC), the latest international video coding standard, greatly outperforms previous standards such as H.264/AVC in terms of coding bitrate and video quality. The coding efficiency improvement in HEVC is achieved by introducing several new techniques such as recursive quad-tree structure and increased number of intra prediction modes. However, computational load is also increased due to employing the new techniques. In this paper, we propose a solution for fast I-frame coding in HEVC standard using homogeneity of Coding Units (CUs). The proposed solution consists of two stages. In the first stage, we evaluate CU homogeneity by computing a parameter named dominant direction strength and predict CU size by this means. In the second stage, we select 11 modes out of 35 for the specified CU size based on dominant direction of the CU. Experimental results indicate that the proposed method achieves on average 45.8 % reduction on coding time, with very similar coding efficiency as the HEVC reference software. Moreover, we designed tree-stage pipelined architecture for our method which can operate at 235 MHz maximum clock rate which means it can be used for real-time coding of all intra configuration of HEVC videos up to level 6.2.