20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

An ultrafast photonic ATM switch based on bit-interleavemultiplexing

An optical ATM switch is proposed in which cells from individual input channels are time-division multiplexed in a bit-interleave manner. This switch can easily handle multicast switching because it is based on a broadcast-and-select network. Compared to an alternative switch that uses a cell-interleave time-division multiplexing scheme, the proposed optical switch has a much simpler structure. It does not need a cell compressor at each input and a cell expander at each output, which greatly reduces hardware complexity. Feasibility analyzes showed that a 64×64 photonic ATM switch with 2.5 Gb/s input/output is possible using the proposed technology. In an experimental demonstration, 4 b cells were selected from a 55 Gb/s bit-interleave multiplexed cell stream by using a new nonlinear optical fiber switch. With its high switch throughput, our switch is a strong candidate for future large-capacity optical switching nodes     

A 100-Gb/s throughput ATM switch MCM with a 320-channel paralleloptical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-μm complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface     

Deep-submicron HEMT technology

The current status of HEMT technology and its impact on computers and communications are presented, focusing on the advantages of the device in the deep-submicrometre dimensional range, self-aligned HEMT processing, and the HEMT LSI implemented in supercomputer and communication systems.

Ultra-low-noise HEMTs are already commercially available in satellite communications, and have made a great impact in expanding the broadcasting satellite market. For ultra-high-speed digital LSI applications the 1 k gate bus-driver logic LSI has been developed to demonstrate high-speed data transfer in a high-speed parallel processing supercomputer system at room temperature, operating at 10·92 Gflops. The 7 k gate asynchronous transfer mode (ATM) switch LSI has alsi been developed to evaluate high-speed data switching for Broadband Integrated Service Digital Network (B-ISDN). The maximum operation frequency was 1·2 GHz at room temperature. The single-chip throughput was 9·6 Gb/s and a throughput of 38·4 Gb/s was achieved in a 4 × 4 ATM switching module.     

Large-scale WDM star-based photonic ATM switches

This paper describes the large-scale photonic asynchronous transfer mode (ATM) switching systems being developed in NTT Laboratories. It uses wavelength division multiplexing (WDM) techniques to attack 1 TB/s throughput. The architecture is a simple star with modular structure and effectively combines optical WDM techniques and electrical control circuits. Recent achievements in important key technologies leading to the realization of large-scale photonic ATM switches based on the architecture are described. We show that we can obtain a 320 Gb/s system that can tolerate the polarization and wavelength dependencies of optical devices. Our experiments using rack-mounted prototypes demonstrate the feasibility of our architecture. The experiments showed stable system operation and high-speed WDM switching capability up to the total optical bandwidth of 12.8 nm, as well as successful 10 Gb/s 4×4 broadcast-and-select and 2.5 Gb/s 16×16 wavelength-routing switch operations     

A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.<>     

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2-μm-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well     

新型光缓存器和2×622Mb／s ATM光交换系统

本文给出一种新型的光缓存器的结构，以解决在ＡＴＭ光交换中的信元碰撞问题。这种缓存器由光纤延迟线、光波导开关阵及非线性半导体光放大器构成。文中还报告了一种用于交换各用户不同速率的信元（可达６２２Ｍｂ／ｓ）的ＡＴＭ光交换实验系统，系统的总容量为１．２Ｇｂ／ｓ。     

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-μm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.     

Ultrafast photonic ATM switch with optical output buffers

An ultrafast photonic asynchronous transfer mode (ATM) (ULPHA) switch based on a time-division broadcast-and-select network with optical output buffers is presented. The ULPHA switch has an ultra-high throughput and excellent traffic characteristics, since it utilizes ultrashort optical pulses for cell signals and avoids cell contentions by novel optical output buffers. Feasibility studies show that an 80×80 ULPHA switch with 1-Gb/s input/output is possible by applying the present technology, and that more than 1 Tb/s is possible by making a three-stage network using such switches. As an experimental demonstration, 4-bit 40-Gb/s optical cells were generated and certain cells were selected at an output on a self-routing basis. With its high throughput and excellent traffic considerations, the ULPHA switch is a strong candidate for a future large-capacity optical switching node     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

On the limits of electronic ATM switching

This article discusses the principal advantages and limitations of electronic switching in asynchronous transfer mode (ATM) networks. Key design parameters of ATM switch implementations are defined, and their relationships with respect to performance, complexity, and cost are modeled and discussed. Design and implementation experience is reported on a very high-performance four-input, four-output ATM switch that has been designed as part of the DARPA-sponsored “Thunder and Lightning” project at the University of California, Santa Barbara. This research project is focused on the design and prototype demonstration of ATM links and electronic switches operating at 40 Gb/s per link (TDM), with potential scalability to 100 Gb/s. Such aggressive link rates are near the implementation limits for electronic ATM switches; they place severe requirements on switch architecture, particularly the buffering scheme     

Breakthrough technologies for the high-performance electrical ATMswitching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8×8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Broadcast-and-select photonic ATM switch with frequency divisionmultiplexed output buffers

A photonic ATM switch has been developed with frequency division multiplexed (FDM) output buffers. The switch has a broadcast-and-select network architecture using fixed-frequency-channel transmitters and a passive star configuration. Although it has a simple structure, it can provide either broadcast or multicast switching. The output buffers, which resolve cell contentions, are comprised of fiber delay lines that can easily handle signal speed of over 10 Gb/s. Experimental switching of two-multiplexed 10 Gb/s cells with a 2.8-dB power penalty demonstrated high-speed switching     

Scalable optoelectronic ATM networks: the iPOINT fully functionaltestbed

Our prototype of a fully-functional asynchronous transfer mode (ATM) switch validates the design of a 128 Gb/s optoelectronic ATM switch. Optoelectronics, rather than all optical components, are used to simultaneously address all of the specific requirements mandated by the ATM protocol. In this paper, we present the Illinois pulsar-based optical interconnect (iPOINT) testbed, and present our results obtained for the prototype switch in a working environment consisting of an optical network of Sun SPARC Stations and other local and wide-area ATM switches