On the effect of bias on the behavior of MOS structures subjected to ionizing radiation

Using a quantitative model [6], the analysis of published data on the effect of the gate bias on the behavior of MOS structure subjected to ionizing radiation is performed. It is shown that, along with hydrogen-containing traps, there are hydrogen-free hole traps in samples with a low content of hydrogen; traps of both types are distributed inhomogeneously over the thickness of the gate insulator. In addition to ionized hydrogen, neutral hydrogen is involved in the formation of surface states and provides the main contribution to this process at negative gate bias. A decrease in the shift of the threshold voltage in the case of high fields is caused by an increase in the drift component of the hole drain to the electrodes.

     

Effect of electron trapping on IGFET characteristics

At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO₂ layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO₂/Si₃N₄ as gate insulator, electron trapping is completely dominated by the Si₃N₄ layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO₂ as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.     

Hot-carrier luminescence in sub-quartermicrometer high-speed GaAsMESFET's

Hot-carrier luminescence in high-speed GaAs MESFET's with sub-quartermicrometer gate length was investigated at drain voltages high enough to permit breakdown. The spectral distribution of emitted radiation was analyzed in the energy range of 1.4-2.5 eV. GaAs MESFET's with a gate length of 0.18 μm yielded a prominent peak from the direct recombination across a GaAs bandgap of 1.43 eV. At energies above 1.65 eV, a broad continuous spectra with two peaks and a shoulder were detected. The two peaks coincide with the indirect recombination energies between holes in the Γ valley and electrons in the L or X valley. These peaks, however, were diminished at drain voltages as high as 7.5 V. It is suggested that the luminescence at energies above the bandgap mainly arises from the recombination of hot carriers, and the luminescence resulting from a phonon-assisted conduction to conduction-band transition is superimposed on it. The luminescence from the gate Schottky diode at reversed bias was also examined. There were no peaks from the direct recombination across the bandgap in the spectra. The light emission at the bandgap energy under the FET operation probably originates from the recombination of cold channel electrons and hot holes, which are generated by impact ionization and swept toward the source     

Hot carrier effects in n-channel polycrystalline silicon thin-filmtransistors: a correlation between off-current and transconductancevariations

The application of bias-stresses with high source-drain voltage and different gate voltages in polycrystalline thin-film transistors modifies the transconductance as well as the off current. These effects have been explained in terms of hot-holes injection into the gate insulator causing the formation of trap centers in the oxide and interface states near the drain     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

Impact ionization and light emission in AlGaAs/GaAs HEMT's

Impact ionization and light emission phenomena have been studied in AlGaAs/GaAs HEMTs biased at high drain voltages by measuring the gate excess current due to holes generated by impact ionization and by analyzing the energy distribution of the light emitted from devices in the 1.1-3.1 eV energy range. The emitted spectra in this energy range can be divided into three energy regions: (i) around 1.4 eV light emission is dominated by band-to-band recombination between cold electrons and holes in GaAs; (ii) in the energy range from 1.5 to 2.6 eV energy distribution of the emitted photons is approximately Maxwellian; and (iii) beyond 2.6 eV the spectra are markedly distorted due to light absorption in the n⁺ GaAs cap layer. The integrated intensity of photons with energies larger than 1.7 eV is proportional to the product of the drain and gate currents. This suggests recombination of channel electrons with holes generated by impact ionization as the dominant emission mechanism of visible light     

AlGaN/GaN 高电子迁移率晶体管在施加阶梯电压应力之后的参数和特性自变化机制

研究了在AlGaN/GaN高电子迁移率晶体管的栅极施加阶梯电压应力之后器件参数和特性的自变化现象。在去除应力之后每5分钟测量一次器件。大信号寄生源（漏）电阻、转移特性、阈值电压、漏源电流、栅-源（漏）反向电流-电压特性在去除应力后发生自发变化。自变化的时间常数大约为25-27分钟。在该过程里,栅-源（漏）电容-电压特性保持稳定。当器件被施加应力时,电子被表面态和AlGaN势垒层陷阱捕获。AlGaN势垒层陷阱所捕获的电子在10秒内释放了出去。表面态释放电子持续发生在整个测量过程中,导致了测量结果的自变化现象。     

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

A new method utilizing Ti—silicide oxidation for the fabrication of a MOSFET with a self-aligned Schottky source/drain

A short and simple fabrication process to realize a MOSFET with a self-aligned Schottky source/drain is described. This process utilizes Ti-silicide deposition and its oxidation, which simultaneously leads to the self-aligning formation of silicided source/drain regions isolated from gate electrodes and the formation of intermediate insulator between Al wire and gate level. The isolation between source/drain and gate has been realized by oxidation at 800°C for 180 min. Sheet resistance of about 4 Ω on the source/drain level has been achieved. This MOSFET has also minimized the "short-channel effect."     

氮化镓基高电子迁移率晶体管Kink效应研究

研究了氮化镓(GaN)基高电子迁移率晶体管(HEMT)发生Kink效应的物理机制,并进行了实验测试。测试结果表明,当第一次扫描、漏极电压较大时,扩散进入耗尽区的电子在高场作用下形成热电子,碰撞电离出深能级施主态中的非平衡电子,第二次扫描的Kink效应减弱。当第一次扫描、漏极电压较小时,扩散进入耗尽区的电子被浅能级缺陷态捕获,第二次扫描的Kink效应增强。在开态下,增大反向栅极电压,可减小沟道电子浓度,进而减小电子捕获效应,Kink效应减弱。在半开态和闭态下,Kink效应不显著。最终得出,GaN缓冲层内类施主型缺陷态对沟道电子的捕获和热电子辅助去捕获,是Kink效应发生的主要原因。     

SiO2 gate insulator defects,spatial distributions,densities, types,and sizes

Standard IC processes, as well as those involving the use of ionizing radiation, such as x-ray lithography etc., result in the generation of bulk defects, and interface states in the gate insulator, or underlying substrate, respectively, of insulated gate field effect transistors. Bulk defects are believed to be present as positively and negatively charged electron and hole traps, respectively, as well as neutral hole and “large” and “small” neutral electron traps. This paper provides a perspective of the current state of knowledge about the spatial distributions of large bulk defects, their areal densities, sizes, possible interrelationships among them, and the special cases of defects created by ion implanted silicon and oxygen, where knock-on effects have been simulated. It appears that bulk defects may all have their origin in neutral hole traps, (so-called E′ centers) and that when the insulator thickness is decreased to about 6-7 nm, defects are either no longer present, or, more likely, are incapable of trapping charge at room temperature because trapped carriers can either tunnel to one of the interfaces, or be annihilated by a reverse process. It appears possible also that the precursor of the several types of defects only forms at a “grown” silicon-silicon oxide interface. In theory, this would make it possible to grow defect free insulators by a combination of deposition and oxidation processes.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

Light‐Emitting Field‐Effect Transistors Consisting of Bilayer‐Crystal Organic Semiconductors

A novel device structure for organic light‐emitting field‐effect transistors has been developed. The devices comprise bilayer‐crystal organic semiconductors of a p‐type and an n‐type. The pn‐junction can readily be formed by successively laminating two crystals on top of a gate insulator. This structure enables the efficient injection and transport of electrons and holes, leading to their effective recombination. As a result, bright emissions are attained. The devices are operated by AC gate voltages. Gate‐voltage phase‐resolved drain‐current and emission‐intensity measurements enable us to study the relationship between the emissions and carrier transport. The maximum external quantum efficiency reaches 0.045%.     

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO2energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to2 times 10^{-4}A/cm². The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.     

The degradation mechanisms in high voltage pLEDMOS transistor with thick gate oxide

The hot-carrier degradation behavior in a high voltage p-type lateral extended drain MOS (pLEDMOS) with thick gate oxide is studied in detail for different stress voltages. The different degradation mechanisms are demonstrated: the interface trap formation in the channel region and injection and trapping of hot electrons in the accumulation and field oxide overlapped drift regions of the pLEDMOS, depending strongly on the applied gate and drain voltage. It will be shown that the injection mechanism gives rise to rather moderate changes of the specific on-resistance (Ron) but tiny changes of the saturation drain current (Idsat) and the threshold voltage (Vth). CP experiments and detailed TCAD simulations are used to support the experimental findings. In this way, the abnormal degradation of the electrical parameters of the pLEDMOS is explained. A novel structure is proposed that the field oxide of the pLEDMOS transistor is used as its gate oxide in order to minish the hot-carrier degradation.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Source-gated thin-film transistors

The thin-film transistor is one of a family of field-effect transistors. They all operate in the same way: a gate modulates the conductance of a channel and the current saturates when the drain end is depleted of carriers. The authors introduce a source-gated transistor that overcomes some of the fundamental limitations of the field-effect transistor. The gate controls the supply of carriers and the current saturates when the source is depleted of carriers. The result is a thin-film transistor that can operate at lower voltages with larger gains and lower power dissipation. It should also preserve its characteristics with smaller dimensions.     

Decrease in on-state gate current of AlGaN/GaN HEMTs by recombination-enhanced defect reaction of generated hot carriers investigated by TCAD simulation

Changes in the on-state gate current of AlGaN/GaN high-electron-mobility transistors (HEMTs) under various electrical and thermal stress conditions have been analyzed by technology computer-aided design (TCAD) simulation. A larger gate current is observed under on-state bias condition than that under off-state bias condition. The TCAD simulation indicates that on-state gate current flows from the heated gate electrode to the AlGaN layer by tunneling or hopping through the gate depletion layer when we apply some deep-donor-type traps under the gate in the AlGaN barrier layer. The gate current is caused by electrons that flow and is pulled away by the applied gate-to-drain voltage under a high channel temperature condition. The deep traps benefit both the on- and off-state gate current behavior. We found that the on-state gate current is effectively decreased by electrical stress under the on-state condition. Electroluminescence measurement indicates that a large number of hot carriers are generated under this condition. The results suggest that the process-induced crystal defects are annealed out by non-radiative recombination of the generated hot carriers by a recombination-enhanced defect reaction mechanism. The change in the on-state gate current in the TCAD simulation can be successfully explained by the decrease in the donor traps.