Hardware based genetic evolution of self-adaptive arbitrary response FIR filters

This work presents a hardware implementation of an FIR filter that is self-adaptive; that responds to arbitrary frequency response landscapes; that has built-in coefficient error tolerance capabilities; and that has a minimal adaptation latency. This hardware design is based on a heuristic genetic algorithm. Experimental results show that the proposed design is more efficient than non-evolutionary designs even for arbitrary response filters. As a byproduct, the paper also presents a novel flow for the complete hardware design of what is termed as an Evolutionary System on Chip (ESoC). With the inclusion of an evolutionary process, the ESoC is a new paradigm in modern System on Chip (SoC) designs. The ESoC methodology could be a very useful structured FPGA/ASIC implementation alternative in many practical applications of FIR filters.     

Handling advanced scheduling heuristics under a hardware compiler generation environment

The complexity of modern digital systems requires complex design entry methods and thus, language based designs are often an appealing alternative for schematics. Language based design entry, supports high-level design transformations through formal and executable traditional compiler construction problem specifications, their main advantages being modularity and declarative notation. In this paper, this idea is exploited under a powerful compiler construction system and a methodology is given to design formal and executable high-level hardware manipulators. In effect, this methodology stands as a meta-level between hardware transformations and their implementation and can be valuable in fast evaluation of new ideas and techniques.     

设计模式在光传输网管系统中的应用研究

设计模式是经过验证可复用的成功设计和体系结构,文中详细地分析了设计模式中的Builder模式、Bridge模式和Command模式在光传输网管系统中的应用,证明了在光传输网管系统中运用设计模式能够有效地提高系统质量、优化系统结构。同时也可以为其他的网管系统所借鉴。     

The Formal Design of 1M-gate ASICs

Refinement of a directory based cache coherence protocol specification, to a pipelined hardware implementation is described. The hardware that is analyzed is the most complex part of a 1M-gate ASIC. The design consists of 30,000 lines of synthesizable register transfer-level verilog code, amounting to approximately 200,000 gates. The design contains a pipeline that is 5 levels deep and approximately 150 bits wide. It has a 16 entry, 150 bit wide, context addressable memory (CAM), and includes a 256 × 72 bit RAM. Refinement maps relate the behavior of the high-level protocol model to the hardware implementation. The Cadence Berkeley Labs SMV model checker was used to create the maps and to prove their correctness. There are approximately 1500 proof obligations. The formal model has been used for three tasks. First, to formally diagnose, and then fix broken features in a legacy version of the design. Second, to integrate the legacy sub-system design with a new system design. Finally, it has been used to formally design additional sub-system features required for the new system design. The same hardware designer enhanced the design, created the refinement maps, and formally proved the correctness of the refinements.     

Knowledge-based automation of a design method for concurrentsystems

This paper describes a knowledge-based approach to automate a software design method for concurrent systems. The approach uses multiple paradigms to represent knowledge embedded in the design method. Semantic data modeling provides the means to represent concepts from a behavioral modeling technique, called Concurrent Object-Based Real-time Analysis (COBRA), which defines system behavior using data/control flow diagrams. Entity-relationship modeling is used to represent a design metamodel based on a design method, called COncurrent Design Approach for Real-Time Systems (CODARTS), which represents concurrent designs as software architecture diagrams, task behavior specifications and module specifications. Production rules provide the mechanism for codifying a set of CODARTS heuristics that can generate concurrent designs based on semantic concepts included in COBRA behavioral models and on entities and relationships included in CODARTS design metamodels. Together, the semantic data model, the entity-relationship model, and the production rules, when encoded using an expert system shell, compose CODA, an automated designer's assistant. CODA is applied to generate 10 concurrent designs for four real-time problems. The paper reports the degree of automation achieved by CODA. The paper also evaluates the quality of generated designs by comparing the similarity between designs produced by CODA and human designs reported in the literature for the same problems. In addition, it compares CODA with four other approaches used to automate software design methods     

Graph grammars for evolutionary 3D design

A new interactive evolutionary 3D design system is presented. The representation is based on graph grammars, a fascinating and powerful formalism in which nodes and edges are iteratively rewritten by rules analogous to those of context-free grammars and shape grammars. The nodes of the resulting derived graph are labelled with Euclidean coordinates: therefore the graph fully represents a 3D beam design. Results from user-guided runs are presented, demonstrating the flexibility of the representation. Comparison with results using an alternative graph representation demonstrates that the graph grammar search space is more rich in organised designs. A set of numerical features are defined over designs. They are shown to be effective in distinguishing between the designs produced by the two representations, and between designs labelled by users as good or bad. The features allow the definition of a non-interactive fitness function in terms of proximity to target feature vectors. In non-interactive experiments with this fitness function, the graph grammar representation out-performs the alternative graph representation, and evolution out-performs random search.     

QuePED: Revisiting queueing networks for the performance evaluation of database designs

Databases form the common component of many software systems. However, performance models specifically targeted at the database design have not been extensively studied. In this paper, we propose QuePED – a queueing network performance evaluation model for database designs. QuePED provides for the performance modelling of database design constructs, including active database rules; thus, deviating from current methods that consider database designs as processing demands on the hardware architecture. We present a formal specification of QuePED and describe its application to database designs. Experimental evaluation has shown the ability of QuePED to capture the steady state performance of an implementation of the TPC-C benchmark.     

AnyBoard: an FPGA-based, reconfigurable system

AnyBoard, a low-cost, field programmable gate array (FPGA)-based, reconfigurable rapid-prototyping system is described. The system hardware organization and software tools that help users automatically map designs to the FPGAs and manage the design process are discussed. The implementation of a pattern generator design is presented to illustrate the system's effectiveness     

基于FPGA的可重构JH算法设计与实现

针对现有可重构JH算法硬件实现方案吞吐量较低的问题,利用查找表方法对S盒进行优化,使改进的JH算法在现场可编程门阵列上实现时具有速度快和面积小的特点,在此基础上提出一种可重构方案。实验结果证明,该方案最高时钟频率可达322.81 MHz,占用 1 405 slices,具有资源占用少、性能参数较好、功耗较低等特点。     

基于FPGA的CIC抽取滤波器设计与实现

现场可编程门阵列（FPGA）器件广泛应用于数字信号处理领域,而使用VHDL或Verilog HDL语言进行设计比较复杂。针对软件无线电中的多速率信号处理技术,提出了一种采用DSP Builder实现级联积分梳状（CIC）抽取滤波器的FPGA实现方案。软件仿真和硬件测试验证了设计的正确性和可行性。     

基于FPGA的卡尔曼滤波器的设计与实现

采用 FPGA 硬件实现卡尔曼滤波器,解决了采用 DSP 软件方法实现存在的并行性和速度问题。以基于 FPGA 的数据采集系统为硬件平台,根据模块化设计思想,采用 VHDL 编程实现ADS8364芯片控制模块,利用 FPGA 的系统级设计工具 DSP Builder 设计卡尔曼滤波器模块,给出模块的软件仿真结果并完成整个系统的硬件验证。结果证明了设计的正确性,同时表明采用 DSP Builder使卡尔曼滤波器的 FPGA 硬件实现更加简单,速度更快。     

平面近场测量系统集成与实现

为满足天线方向图的平面近场测量[1-2],设计了一套功能强大的自动平面近场测量系统;在硬件方面采用了分布式的搭建形式,而在软件方面则使用了Borland C++Builder 6.0[3]和Matlab7.0并采用模块化、层次化的软件集成方式,提高了软件的可维护性,缩短了开发周期;该系统实现了0.1～18GHz频带下,对天线方向图的平面近场测量,并同时进行数据的接收、处理、分析和显示;该系统丰富的功能为天线(阵列)方向图的测量[4-5]提供了强大的测试平台。     

Design and implementation of a lossless parallel high-speed data compression system

Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.     

Specification and Standardization of a Java Trusted Computing API

The paradigm of Trusted Computing promises a new approach to improve the security of computer systems. The core functionality, based on a hardware component known as Trusted Platform Module, is integrated into commodity hardware. However, operating system integration and application software support remains limited at present. In particular, for Java, the most widely used platform‐independent computing environment, there is currently no generally accepted Trusted Computing API. In this article, we describe the design of a high‐level API for Trusted Computing. We report on the current state of the Trusted Computing Group's software architecture and on previous approaches targeting Java. We derive our requirements and design goals and describe a novel API design. We report on our transparent approach to standardization in the Java Community Process. The result of this effort is the API we propose in the Java Specification Request 321. In this work, we not only present the design of this new API but also discuss implementation and testing strategies. Copyright © 2011 John Wiley & Sons, Ltd.     

企业服务总线在企业应用集成中的研究与应用

企业应用集成(EAI)是通过硬件,软件,标准和业务过程的结合,实现两个或多个企业系统之间的无缝集成,使它们能够统一运作.介绍了面向服务体系架构(SOA),并结合企业服务总线(ESB)技术,提出了一种新的企业应用集成框架.同时,给出了基于Mule ESB的EAI框架中商品价格查询实例的设计与实现.     

Hardware/software cost analysis of interrupt processing strategies

A new study compares the architectural design and implementation costs of five strategies that let pipelined processors support precise interrupts. Hardware dominates the cost of all strategies except checkpoint repair, which, depending on the implementation, can incur either high software or hardware costs     

Design,implementation and analysis of hardware efficient stream ciphers using LFSR based hash functions

Design and implementation of hardware efficient stream ciphers using hash functions and analysis of their periodicity and security are presented in this paper. The hash generation circuits used for the design and development of stream ciphers are low power, low hardware complexity Linear Feedback Shift Register (LFSR) based circuits. One stream cipher design uses LFSR based Toeplitz hash generation circuit together with LFSR keystream generator circuit, while the other design combines LFSR based filter generator circuit with LFSR based polynomial modular division circuit. Both designs possess good security and periodicity properties for the keystreams generated. The developed circuits can compete with the most popular classic LFSR based stream ciphers in hardware complexity at the same time providing additional advantage that the same circuit can be used for hash generation.     

基于网络处理器的防火墙流量控制技术

分析了流量控制机制中现有的缓冲管理和分组调度算法,提出一种适合防火墙流量控制特点和网络处理器特点的自适应抢夺式流量控制算法,并给出基于网络处理器IXP2400的具体设计实现。     

基于DSPBuilder的双三次插值算法FPGA实现的研究

研究利用DSPBuilder来完成DSP算法在FPGA上实现的方法，与传统的DSP技术相比，FPGA在实现DSP功能上其并行设计的灵活性和高效性更具优势，研究的设计方法解决了在FPGA上通过编写硬件描述语言（HDL）实现DSP算法的设计难度大、开发周期长2个问题，在此以双三次插值算法为例，研究了这种方法的可行性。