Plastic packaging is highly reliable

Plastic encapsulation is now a high reliability (HiRel) method of packaging active semiconductor devices and microelectronics in general. This paper shows that the traditional requirement for hermetic packaging can be overturned in favor of plastic packaging, on the following grounds: the full range of laboratory evidence of HiRel silicone junction coated IC undertaken by many researchers, showing that plastic encapsulations can now be used for microelectronics and optoelectronics in telecommunication, automotive, military and space applications as the better option in many instances; the inadequacy of the Mil-Std hermeticity specification; the demonstrated field failures of Mil-Std-883 hermetic packaged devices and the massive ingress of moisture, which caused many failures of telecommunication switching systems; and the demonstrated better field-reliability in rural tropical climates, of assessed, standard PEM from major manufacturers     

Recent advances in plastic packaging of flip-chip and multichipmodules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications     

A Reliability Evaluation of Plastic Packaged Semiconductor Components

Qualification testing programs have been developed for assessing the reliability of commercial grade discrete semiconductors for use in office business machines. These programs include accelerated stresses of high temperature storage (HTS) and high temperature reverse bias (HTRB) for 1000 hours, and a sequence test of thermal cycle and thermal shock followed by storage at 85°C and 85% RH (85/85) for 1000 hours. Both hermetic and plastic encapsulated parts have been tested more than 15 million part hours. HTRB and 85/85 are about twice as effective as HTS in identifying potentially unreliable parts. Plastic packaged semiconductors are inherently capable of withstanding 85/85 for 1000 hours without parameter degradation. The value of qualification testing against the 85/85 environment is demonstrated by the observed correlation of machine failure rates in the field with the relative humidity in the use environment. The observed failure rate of plastic parts is not more than 3.2 times that of hermetic parts. Plastic parts are capable of reliable operation, but the marked differences in reliability between different vendors and between different part types from the same vendor require increased process and materials control in order to achieve the potential of which plastic parts are capable.     

Quasi hermetic packaging for new generation of spaceborn microwave equipment

This paper presents the introduction of the quasi hermetic encapsulation of microwave hybrids for space application through different approaches evaluated at Thales Alenia Space – France. Thanks to the improvement for many years of microwave organic materials, it is now realistic to propose advanced packaging solutions like the chip on board approach with glob top encapsulation of active devices directly bonded on printed circuit boards for space applications. To validate this packaging approach, very significant reliability test-plans have been proposed and performed on the different technological processes and materials in agreement with standard space quality requirements. Results will be presented and a discussion on the nature of the stresses applied during the tests will be proposed.     

Sources and control of volatile gases hazardous to hermeticelectronic enclosures

Four gases that threaten operating reliability may be present in hermetic electronic enclosures. Condensates of moisture and/or ammonia can cause metallization corrosion. Hydrogen is a rapid diffuser that can degrade metal-oxide-semiconductor (MOS) device operation. Oxygen can cause oxidation and ensuing failure of solder attachment materials within the sealed package. Other gases, such as carbon dioxide, helium, argon, and organic volatiles are not threats to reliability, but do provide clues to package materials behavior. Knowing sealed package ambient gas composition helps improve materials and processes for hermetic sealing and enables process control to assure reliable products. This paper describes the analysis method for hermetic microelectronics, residual gas analysis (RGA), available at only a few laboratories worldwide. It discusses sealing processes and package piece part materials that are sources of volatiles hazardous to product reliability. It presents materials selection and improvement considerations to reduce and control dangerous volatiles in hermetic packages     

Reliability of new packaging concepts

Today, most of the microelectronics packaging needs are met by semiconductor devices in plastic surface mount (SM) packages. Microelectronics packaging of the future will be either bare chip or chip size/scale packaging (CSP). Of the 45 billion SM packaged ICs to be manufactured in 2000, CSPs will be a small 3.4% but growing at 62% (compound annual growth rate). The use of direct bonded chip-on-board and flip chip (FC) technology for custom solutions may not match the growth of CSPs. The popcorn problem of existing plastic packages has been solved in many ways including the use of hydrophobic composite encapsulants as the best solution and thorough bake-out and storage as the long-standing practical solution. The popcorn problem which was more severe with the smaller and thinner encapsulations of CSPs is also solved with modern hydrophobic materials and new non-paddle package designs. Further, there is good evidence that reliability is not impaired even by delaminations in the bulk of the encapsulations – small delaminations being an inevitable consequence of stress relaxation following transfer moulding. CSP and FC bump joint reliability is safeguarded both by good soldering practice and by effective underfill. High reliabilities are achievable with the range of new packages built from modern materials, with random failure rates down to 10 failure units, infant mortalities controlled to low levels by six sigma manufacturing processes and wearout lifetimes exceeding 100 years even in tropical operation.     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Non-destructive identification of defects in integrated circuit packages by scanning acoustic microscopy

Scanning acoustic microscopy (SAM) has emerged as a powerful tool for the detection of defects in ceramic or plastic packaged integrated circuits. At the Singapore Institute of Standards and Industrial Research, we have been using SAM to identify packaging and/or assembly related defects across a broad spectrum of integrated circuit packages. In many cases, it has been the only technology available that is capable of quickly and non-destructively determining the precise failure mode, such as delamination.     

The reliability of laser diodes and laser transmitter modules

This paper reviews the reliability of laser transmitter modules for use in optical fibre transmission systems. Methods for reliability testing and lifetime prediction are discussed and the dominant failure mechanisms affecting laser modules are described. The current status of laser module reliability is discussed, based on both published results, and on the findings of a study at BT Laboratories of the reliability of commercial laser modules from ten manufacturers. It is concluded that significant progress has been made in the reliability of laser diodes, through the understanding of basic failure mechanisms, leading to long predicted lifetimes for a number of different laser structures. However, module packaging is less reliable and further work is required to identify and eliminate those materials and processing technologies which lead to the risk of early failure.     

High-reliability 1.3-μm InP-based uncooled lasers in nonhermeticpackages

We report the first uncooled nonhermetic 1.3-μm InP-based communication lasers that have reliability comparable to their hermetically packaged counterparts for possible applications in fiber in the loop and cable TV. The development of reliable nonhermetic semiconductor lasers would not only lead to the elimination of the costs specifically associated with hermetic packaging but also lead the way for possible revolutionary low-cost optoelectronic packaging technologies. We have used Fabry-Perot capped mesa buried-heterostructure (CMBH) uncooled lasers with both bulk and MQW active regions grown on n-type InP substrates by VPE and MOCVD. We find that the proper dielectric facet passivation is the key to obtain high reliability in a nonhermetic environment. The passivation protects the laser from the ambient and maintains the proper facet reflectivity to achieve desired laser characteristics. The SiO facet passivation formed by molecular beam deposition (MBD) has resulted in lasers with lifetimes well in excess of the reliability goal of 3,000 hours of operation at 85°C/90% RH/30 mA aging condition. Based on extrapolations derived experimentally, we calculate a 15-year-average device hazard rate of <300 FITs (as against the desired 1,500 FITs) for the combination of thermal-and humidity-induced degradation at an ambient condition of 45°C/50% RH. For comparison, the average hazard rate at 45°C and 15 years of service is approximately 250 FITs for hermetic lasers of similar construction. A comparison of the thermal-only degradation (hermetic) to the thermal plus humidity-induced degradation (nonhermetic) indicates that the reliability of these nonhermetic lasers is controlled by thermal degradation only and not by moisture-induced degradation. In addition to device passivation for a nonhermetic environment, MBD-SiO maintains the optical, electrical, and mechanical properties needed for high-performance laser systems     

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Cu–Cu Hermetic Seal Enhancement Using Self-Assembled Monolayer Passivation

Low-temperature Cu–Cu thermocompression bonding enabled by self-assembled monolayer (SAM) passivation for hermetic sealing application is investigated in this work. Cavities are etched to a volume of 1.4 × 10^?3 cm³ in accordance with the MIL-STD-883E standard prescribed for microelectronics packaging. The wafer pairs (nonfunctional cavity wafer and cap wafer) are annealed and bonded at 250°C under a bonding force of 5500 N. The encapsulated cavities undergo helium overpressure in a bombing chamber, and the helium leak rate is detected by a mass spectrometer. The measurement results show that the cavities sealed with Cu–Cu bonding after SAM passivation exhibit excellent hermeticity with a leak rate below 10^?9 atm cm³/s, which is an improvement of at least 2× compared with the control sample without SAM passivation.     

Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Material property effects on solder failure analyses

The effects of material properties modeling on the solder failure analyses by numerical simulations are studied. The packaging structure of plastic ball grid array on printed circuit board was modeled. Two different types of molding compounds and two different types of substrates were employed and combined for the plastic ball grid array package modeling. The material properties were assumed as temperature dependent elastic and viscoelastic, and finite element method was used to calculate and analyze the strain energy densities of the solder balls. The chip warpage was also studied, and related with the solder ball reliability analyses by discussing the viscoelastic characteristics of the materials and their influences on the deformations. The results showed that the warpage developments of the packaging structure showed very different behaviors, and the mechanism of the strain energy density accumulations in the solder balls were also different depending on the material properties modeling and their combinations. This study demonstrates that appropriate modeling of the material properties is critical for the interpretation and understanding the microelectronics reliability mechanisms.     

电子元器件可靠性增长的分析技术

从元器件可靠性物理分析技术角度,系统地阐述了失效信息的收集与分析、失效分析、破坏性物理分析、密封器件内部气氛分析、失效模式及机理与工艺的相关性分析、失效模式与影响分析等元器件的质量与可靠性分析技术。将元器件质量与可靠性分析技术融入元器件产品设计、制造过程是实现元器件可靠性增长的必然趋势。     

大功率白光LED封装设计与研究进展

封装设计、材料和结构的不断创新使发光二极管(LED)性能不断提高.从光学、热学、电学、机械、可靠性等方面,详细评述了大功率白光LED封装的设计和研究进展,并对封装材料和工艺进行了具体介绍.提出LED的封装设计应与芯片设计同时进行,并且需要对光、热、电、结构等性能统一考虑.在封装过程中,虽然材料(散热基板、荧光粉、灌封胶)选择很重要,但封装工艺(界面热阻、封装应力)对LED光效和可靠性影响也很大.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物。COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连。研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响最小。对用于标准的COF工艺的融除程序进行分析和特征描述,以便设计一种新的对裸露的MEMS器件热损坏的潜在性最小的程序。COF/MEMS封装技术非常适合于诸如微光学及无线射频器件等很多微系统封装的应用。     

The application of lead-free solder to optical fiber packaging

To achieve precise, hermetic, and reliable optoelectronic packaging, we studied a novel technology for bonding fibers to v-grooved chips by metallic soldering. Multilayered metallization of Ti/Au, Ti/Cu/Au, or Ti/Ni/Au has been prepared to improve the poor bonding nature of solder on oxide surface. The eutectic 43Sn57Bi (wt.%) alloy, having a melting point of 139°C, was selected to bond the fibers to v-grooved chips. The alignment and adhesion tests result show that the precision packaging by soldering has a satisfied reliability in the range of working temperature from −40°C to 85°C. The metallic solder bonding is hermetic, and hence, it can isolate the optical device from ambient environment.     

Characterisation of chip-on-board and flip chip packaging technologies by acoustic microscopy

In recent years scanning acoustic microscopy (SAM) has been found to be a very successful technique when used in the microelectronics industry to evaluate, from a reliability perspective, standard plastic packaging technologies such as PQFP's, PLCC's, DIP's and SOP's. Very little research has been reported in the application of SAM as a technique for determining the quality and reliability of packaging technologies such as Chipon-Board (COB) and Flip Chip adhered devices, however. These areas will be addressed in this paper.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物.COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连.研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响...