Power-delay-area efficient modulo 2/sup n/+1 adder architecture for RNS

A new modulo 2/sup n/+1 adder architecture based on the ELM addition algorithm is introduced. A simplification to an existing modulo 2/sup n/+1 addition algorithm is also presented. VLSI implementations using 130 nm CMOS technology demonstrate the superiority of the proposed adder over existing designs in the literature.     

An efficient VLSI design for a residue to binary converter for general balance moduli (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3)

In this paper, we present a new four-moduli set (2/sup n/-3,2/sup n/+1,2/sup n/-1,2/sup n/+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.     

An efficient tree architecture for modulo 2 n +1 multiplication

Modulo 2 ⁿ +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2 ⁿ +1) multiplication either use recursive modulo (2 ⁿ +1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2 ⁿ +1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.     

An efficient tree architecture for modulo 2n+1 multiplication

Modulo 2 ⁿ +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2 ⁿ +1) multiplication either use recursive modulo (2 ⁿ +1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2 ⁿ +1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.     

Low complexity bit-parallel normal bases multipliers for GF(2/sup n/)

Based on the divide-and-conquer technique, three bit-parallel normal bases multipliers are presented for GF(2/sup n/). The space complexity of one multiplier is about 3/4 of the smallest known normal bases multiplier, although it needs at most one more XOR gate delay.     

Addition-based exponentiation modulo 2/sup k/

A novel method for performing exponentiation modulo 2/sup k/ is described. The algorithm has a critical path consisting of k dependent shift-and-add modulo 2/sup k/ operations. Although 3 is the preferred exponent base, the algorithm can be extended easily in order to perform the general binary powering operation.     

Key function of normal basis multipliers in GR(2/sup n/)

A new definition of the key function in GF(2/sup n/) is given. Based on this definition, a method to speed up software implementations of the normal basis multiplication is presented. It is also shown that the normal basis with maximum complexity can be used to design low complexity multipliers. In particular, it is shown that the circuit complexity of a type I optimal normal basis multiplier can be further reduced.     

Additive bit-serial algorithm for discrete logarithm modulo 2/sup k/

A novel algorithm for computing the discrete logarithm modulo 2/sup k/ that is suitable for fast software or hardware implementation is described. The chosen preferred implementation is based on a linear-time multiplier-less method and has a critical path of less than k modulo 2/sup k/ shift-and-add operations.     

On MultiModuli residue number systems with moduli of forms r/sup a/, r/sup b/-1, r/sup c/+1

The residue number system (RNS) is an integer system appropriate for implementing fast digital signal processors since it can support parallel, carry-free, high-speed arithmetic. One of the most important considerations when designing RNS systems is the choice of the moduli set. This is due to the fact that the system's speed, its dynamic range, as well as its hardware complexity depend on both the forms and the number of the chosen moduli. When performing high radix-r(r>2) arithmetic, moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 imply simple RNS arithmetic and efficient weighted (radix-r)-to-RNS and RNS-to-weighted (radix-r) conversions. In this paper, new multimoduli high radix-r RNS systems based on moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are presented. These systems will be derived from some recently developed theory. Such systems including moduli of forms r/sup a/, r/sup b/-1 and r/sup c/+1 are appropriate for multiple-valued logic implementations or high radix (r>2) arithmetic using binary logic. The new RNS systems are balanced, achieve fast and simple RNS computations and conversions and implement large dynamic ranges. The specific case of the binary (radix r=2) domain is also presented.     

Spectrally efficient full-response Q/sup 2/PSK signals

Based on a novel class of orthogonal pulse pairs, a spectrally efficient full-response quadrature-quadrature phase-shift keying (Q/sup 2/PSK) signal format is proposed. The proposed full-response Q/sup 2/PSK signals can provide higher spectral compactness than conventional full-response Q/sup 2/PSK signal, minimum-shift keying signal and quadrature phase-shift keying signal.     

Handling zero in diminished-one modulo 2 n + 1 adders

Zero treatment in diminished-one modulo 2 ⁿ + 1 addition has traditionally been performed separately, leading to slow and area-consuming implementations. To overcome this, on the basis of an enhanced number representation used previously, we introduce novel carry look ahead and parallel-prefix architectures for diminished-one modulo 2 ⁿ + 1 adders that can also handle operands equal to 0. Translators for the new representation are also given.     

Normal basis multiplication algorithm for GF(2/sup n/)

A normal basis multiplication algorithm is presented. Its complexity depends on the multiplicative order of the normal element.     

2/sup 1///sub 2/ step flash A/D convertor

A simple technique for obtaining an extra bit of resolution from a multistep flash A/D convertor is described. It is shown that when used with a conventional multistep convertor, this technique can give significant savings in chip area and power at the expense of a very small increase in conversion time.<>     

A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can be divided into four categories.. A watermark is a secondary translucent image overlaid into the primary image and appears to a viewer on a careful inspection. The in watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This paper presents a new very large scale integration (VLSI) architecture for implementing two digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework. To the authors' knowledge, this is the first VLSI architecture for implementing watermarking schemes. A prototype chip consisting of 28 469 gates is implemented using 0.35-/spl mu/ technology, which consumes 6.9-mW power while operating at 292 MHz.     

An architecture for high-performance/small-area multipliers for usein digital filtering applications

A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier's partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an ll-b by ll-b multiplier using second-order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm². Also, an ll-b by 16-b multiplier using third-order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm² and it operates in 19 ns     

n/sup k/-pulse position modulation for optical wireless communication

An original analysis is presented for n/sup k/-PPM in which the information is conveyed by the position of k pulses, each within their own frame of n slots, giving n/sup k/ PPM symbols. Comparisons are made with multiple PPM (MPPM) and it is demonstrated that n/sup k/-PPM offers improved orthogonality, a simplified circuit implementation and comparable receiver sensitivity.     

Fast algorithms for determining the linear complexity of sequences over GF(p/sup m/) with period 2/sup t/n

We prove a result which reduces the computation of the linear complexity of a sequence over GF(p^m) (p is an odd prime) with period 2n (n is a positive integer such that there exists an element bisinGF(p^m), bⁿ=-1) to the computation of the linear complexities of two sequences with period n. By combining with some known algorithms such as the Berlekamp-Massey algorithm and the Games-Chan algorithm we can determine the linear complexity of any sequence over GF(p^m) with period 2^tn (such that 2 ^t|p^m-1 and gcd(n,p^m-1)=1) more efficiently     

Synthesis of single sets of 2/sup n/ mutually orthogonal phase codes

Unique sets of 2/sup n/ phase coded pulses are introduced. Derived from any phase code, using simple transformations, these codes possess the useful property that the sum of all possible cross-correlations added to the sum of all autocorrelations within a set produces a pulse compressed signal. This signal has a peak to sidelobe ratio equal to that for the autocorrelation function of the original untransformed code.<>     

New fast algorithm for two-dimensional discrete Fourier transform DFT (2/sup n/; 2)

Presents a new fast algorithm for computing the two-dimensional discrete Fourier transform DFT(2/sup n/; 2) using the fast discrete cosine transform algorithm. The algorithm has a lower number of multiplications and additions compared with other published algorithms for computing the two-dimensional DFT. Because it uses only real multiplications, the algorithm is more suitable for real input data.<>