并行预处理有限元方法及其在系统级封装结构电磁模拟中的应用

针对系统级封装结构的电磁兼容、信号完整性分析等应用,由于结构的复杂、多尺度和多材料的特性,其大规模电磁问题模拟一直难以实现.本文中,主要展示了基于并行支撑框架JAUMIN研发的高性能电磁计算程序JEMS-CDS及其在系统级封装结构电磁仿真中采用的高效算法.针对系统级封装结构电磁仿真,我们构建了两种预处理技术:区域分解方...     

集成两路射频SiP发射器的设计和研究

随着移动通信和其它电子应用领域的不断进步,系统集成需求日益紧迫。除了可以应对系统性能、功能、成本和小型化的更高要求,系统级封装(SiP)在降低开发成本、实施灵活设计、缩短开发周期,和集成异质芯片上也有突出优势。这篇文章介绍了一个可用于手机基站系统的双通路发射系统SiP模块的开发。我们用计算模拟方法辅助优化设计,并成功制造和验证了SiP模块。SiP为内嵌电磁干扰屏蔽罩的12mmx12mmx1.9mm的多层栅格阵列封装(LGA)。各种射频信号性能均通过测试,包括严格的隔离度要求。电磁屏蔽测试和计算模拟结果高度吻合。最后,文章介绍了一种高效的计算模拟方法,极大地缩短了计算模拟的时间,并对未来射频SiP开发将提供有力帮助。     

SOC系统设计技术发展与挑战

从SOC技术的基本概念和设计流程出发,介绍了SOC设计的关键技术,讨论了SOC在设计方法,工艺实现和性能测试等方面的技术挑战。同时展望了SOC技术的发展趋势,阐述了SiP技术与SOC技术的相关关系及SiP的技术优势。     

高速数字电路中的信号完整性分析

在高速数字电路设计中,随着电子产品的不断更新换代,其系统主频变得越来越高和产品变得越来越小型化,板级互连线的信号完整性问题也越来越突出。针对高速数字电路设计中的反射和串扰等信号完整性问题,分析破坏信号完整性的原因,并提供改善信号完整性的方法：采用端接技术和增加敏感信号线的间距。通过采用Hyperlynx仿真工具对在SC...     

高速电路中的信号完整性及仿真

为在高速数字系统设计中,随着数字电路工作频率的提高,信号完整性问题变得无处不在,对电路稳定性影响巨大。针对高速PCB设计要求讨论了设计中涉及的延迟、反射、串扰等信号完整性问题,分析了各种破坏信号完整性的原因,并提供了改善信号完整性的对策。通过采用Cadence/SpecctraQuest仿真工具对一ARM9核心板电路板中的高速SDRAM时钟信号线的布局布线后的仿真,给处了由于没有阻抗不匹配造成设计失败的实例,重点分析了高速电路板中存在的阻抗匹配问题,并给出了利用Cadence/SpecctraQuest解决信号完整性问题办法。     

在Protel DXP中进行信号完整性问题分析

随着各种大规模、高密度的新型电子元器件的不断涌现,电路板的设计变得越来越复杂,信号完整性已成为PCB设计必须关心的问题之一。这里,介绍了Protel DXP中的信号完整性（SI）分析工具,并详细说明如何利用Protel DXP的信号完整性分析功能进行印制电路板的设计,从而改善电路设计。     

SiP协调设计与PI解析(1)

概述了SiP协调设计和PI解析: (1)SiP与协调设计,(2)SiP的形态.     

一款微处理器芯片电源网络的验证及优化

当CMOS工艺进入深亚微米设计阶段,器件密度和时钟频率增加,电源线和地线网络传送的电流也同样增加,导致功率密度的增加,这些都将对电源网络产生不利影响。因此,设计良好的电源网络显得尤为重要。为了确保较短的设计周期以及满足可靠性和可制造性的要求,电源网络的验证及优化已成为整个设计流程中关键的一步。首先介绍了存在于电源网络的欧姆电压效应,并且给出了一款系统芯片的电源网络的验证优化流程,基于此流程进行欧姆压降的分析,在尽量缩小设计周期的考虑下,给出了优化的几个方法,并应用于工程实际,达到了设计要求。     

深亚微米IC物理设计流程中的串扰控制

信号完整性的设计收敛已经成为当前深亚微米集成电路物理设计流程中的关键问题。对信号完整性收敛产生不利影响的有三个因素：串扰、直流电压降和电迁移。其中影响最大的是串扰,串扰噪声会产生大量的时序违规、逻辑错误。主要关注基于串扰控制的物理设计方法,包括新的流程、各个设计阶段对串扰的分析及修正的方法,以达到快速的时序收敛。并且根据真实的设计实例,提出了几点有效的控制串扰的方法和对于信号完整性管理比较有价值的观点。     

基于SiP技术的胶囊内窥镜微型电路系统制造

胶囊内窥镜是近年发展起来的微型医疗仪器,其电路构造具有体积小、功能全等特点。文章提出用高密度封装SiP技术实现胶囊内窥镜的电路系统微型化。相对传统的芯片定制方式,采用堆叠式、表面贴装式或倒装焊式等组装方式具有成本低、难度低、开发周期短的优点。SiP封装、埋植式元件基板制造等高密度封装技术的不断发展,使得采用普通商用芯片实现胶囊内窥镜电路系统制造具有可行性。     

Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs

Compared with traditional flow in IC designs, the assignment of the inter-die signals between different dies is an important stage in a die-stacking SiP design. In this paper, given a tolerant spacing rule between two inter-die signals, the crossing constraint between two inter-die signals can be firstly defined for the bonding wires in a die-stacking SiP design with a simplified wiring model [7]. Furthermore, based on the connection constraint on any inter-die signal, the capacity constraint on any assigned pad on dies and the crossing constraint between two inter-die signals, an integer linear programming-based (ILP-based) approach is proposed to assign all the inter-die signals to minimize the total wirelength in a die-stacking SiP design. Compared with Lin’s two-stage approach [4] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach increases 4.5% of CPU time and reduces 6.2% of total wirelength to assign all the inter-die signals on the average. Besides that, compared with Yan’s iterative approach [6] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach uses reasonable CPU time to reduce 5.3% of total wirelength to assign all the inter-die signals on the average. Compared with Lin’s modified two-stage approach and Yan’s modified iterative approach for some dense tested examples with a tolerant spacing distance between two inter-die signals in a simplified wiring model [7], the experimental results show that Lin’s modified two-stage approach only achieves 95.9% of the assignment ratio on the average, Yan’s modified iterative approach only achieves 96.6% of the assignment ratio on the average and our proposed ILP-based approach uses reasonable CPU time to achieve 100% of the assignment ratio.     

一种基于SiP技术的加速度计有源磁悬浮控制电路

加速度计是以加速度的观点来测量物体运动的传感器,它通过检测质量块的惯性力来测量载体的线加速度或角加速度。文中介绍的有源磁悬浮控制电路与陀螺浮子构成磁悬浮摆式积分陀螺加速度计,该加速度计具有量程大、测量精度高等优点。受整机系统内部装配空间的限制,在电路集成化产品的设计中,采用系统集成封装(SiP)技术设计与制作有源磁悬浮控制电路,减小电路产品的底面积和高度,适应整机系统对产品的装配和使用要求。同时详细介绍了基于SiP技术的电路设计方法,对HTCC工艺的SiP结构设计进行了阐述,并简述了HTCC工艺的SiP产品达到的技术性能和应用情况。     

平行传输线间串扰的仿真及分析

在高速电路设计中,信号完整性问题越来越突出,已经成为高速电路设计师不可避免的问题。该文重点研究了平行传输线间的串扰问题,通过信号完整性分析软件Hyperlynx建立了三线串扰模型并进行仿真分析,最后提出高速PCB设计中减小串扰噪声的策略。     

递进型射频SiP系统优化法研究

射频系统级封装系统具有高密度集成、高性能的优点,但其电磁问题复杂导致系统优化方法至关重要。基于板级场路协同仿真、近场等效模拟以及近场扫描测试,提出了递进型射频SiP系统优化方法,并以S波段上变频SiP模块的优化为例,进行了验证分析。利用此方法,准确地找到了系统中潜在的风险,建立近场耦合等效集总电路,提出改进措施,实现了系统的高效优化;并采用近场扫描测试方法,对模拟结果进行了比较,计算出两者的相关度为96.27%,吻合较好,证明了模拟仿真优化法的高可靠性与实用性。     

The defensive design of printed-circuit boards

This article on signal integrity has been approached from a slightly different angle than that normally pursued. There is an abundance of material on general signal integrity. Instead of repeating textbook techniques, however, the focus has been on two important issues: visualization, to assist intuition; and the basics of defensive design, which helps the designer get his or her design right the first time and allows some minor mistakes. The techniques described generally relate to digital boards using a fundamental frequency that is typically up to 2 GHz with signal transition times as low as 0.1 ns. Field solvers and ground planes are discussed as are connections and EMC aspects.     

基于系统级封装(SiP)的信息安全芯片集成设计

为了解决信息安全系统中,逻辑运算芯片与存储器难以实现集成的问题,并更充分地满足信息安全系统高性能、低功耗、高可靠性的要求,本文提出了"基于SiP的信息安全芯片集成"的概念及具体设计方案.根据此方案设计实现了一款集成CPU、Flash存储器、密码算法芯片的小型信息安全系统的SiP成品实例,该成品的功能和性能验证结果均满足系统的目标需求,从而证实了该设计方案的可行性.该方案也符合今后电子技术和信息安全系统的主要发展方向.     

Using metro-on-chip in physical design flow for congestion and routability improvement

Routability, signal integrity and manufacturability are important issues in physical design and congestion reduction is a widely used method for ameliorating these problems in current design methodologies. Besides, routing congestion may create large delays in detoured global wires that can be avoided by congestion reduction. In recent years, asynchronous serial transceivers are proposed for data transmission in network-on-chip systems to improve the performance of global wires. However the asynchronous transceivers have not been used for reducing the congestion and improving the routability in the physical design flow.In this paper, a new methodology is presented in which regular nets are multiplexed by asynchronous serial transceivers in the physical design flow in order to improve routing congestion and design routability. Experimental results show that for attempted benchmarks, the congestion is reduced by 18.97%, the routability is increased by 21.57% on average and total wirelength is decreased up to 9.05%. However, the overhead in power consumption and computation time are 0.12% and 10.01%, respectively, on average.     

Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications

A new floating-gate (FG) MOSFET based wireless dosimeter system-in-package (SiP) is presented. This miniature and completely integrated wireless dosimeter SiP comprises a CMOS FG radiation sensor and transmitter (TX) in a low-temperature co-fired ceramic (LTCC) package. The design is very well suited to wireless transmission of radiation sensor data in radiotherapy and to Extra Vehicular Activity Radiation Monitoring (EVARM) in space. Two different solutions, namely system-on-chip (SoC) and SiP, are demonstrated. In the SoC, which is size and power efficient, the TX includes an on-chip loop antenna which also acts as the inductor for the VCO resonant tank circuit. The SiP solution has an LTCC antenna with optimized impedance to conjugate match the TX chip. The radiation sensor demonstrates a measured sensitivity of 5 mV/rad. The SoC module size is only 2 ${hbox {mm}}^{2}$, consumes 5.3 mW of power and delivers $-$0.9 dBm of radiated power, sufficient to communicate with a low noise receiver connected to an off-chip patch antenna placed 1.38 m away. The SiP design provides a larger communication range of 75 m at the cost of additional power consumption and size.      

Fast reliability qualification of SiP products

For the purpose of rapidly identifying the functional weak points of SiP products and defining appropriate design rules, a new methodology is proposed to achieve fast reliability qualification. This new methodology is based on the moisture absorption behavior along the critical interface of a SiP carrier and on the most sensitive zone to delamination of the SiP carrier, determined by simulation and experimentally checked. In this paper, a new accelerated preconditioning is proposed and a new non destructive thermal method to monitor the delamination is presented. The effectiveness of this new stress test to accelerate the failure mechanism of the SiP carrier and the ability to detect delamination are evaluated by performing a DOE.     

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era

“More than Moore” is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach—SiP or SoC—before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.