Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.     

堆叠栅介质MOS器件栅极漏电流的计算模型

采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.     

恒压应力下超薄Si_3N_4/SiO_2叠层栅介质与SiO_2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Photo-CVD SiO/sub 2/ layers on AlGaN and AlGaN-GaN MOSHFET

High-quality SiO/sub 2/ was successfully deposited onto AlGaN by photochemical vapor deposition (photo-CVD) using a D/sub 2/ lamp as the excitation source. The resulting interface state density was only 1.1 /spl times/ 10/sup 11/ cm/sup -2/eV/sup -1/, and the oxide leakage current was dominated by Poole-Frenkel emission. Compared with AlGaN-GaN metal-semiconductor HFET (MESHFETs) with similar structure, the gate leakage current is reduced by more than four orders of magnitude by using the photo-CVD oxide layer as gate oxide in AlGaN-GaN metal-oxide-semiconductor heterojunction field-effect transistors (MOSHFETs). With a 2-/spl mu/m gate, the saturated I/sub ds/, maximum g/sub m/ and gate voltage swing (GVS) of the fabricated nitride-based MOSHFET were 572 mA/mm, 68 mS/mm, and 8 V, respectively.     

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

The low-frequency noise has been studied in nMOSFETs with an HfO/sub 2/--SiO/sub 2/ gate stack, for different thickness of the SiO/sub 2/ interfacial layer (IL). It is observed that the 1/f-like noise in linear operation, is about 50 times higher in the HfO/sub 2/ devices with a 0.8-nm chemical oxide IL, compared with the 4.5-nm thermal oxide reference n-channel transistors. This is shown to relate to the correspondingly higher trap density in the dielectric material. In addition, it is demonstrated that the noise rapidly reduces with increasing thickness of the IL. From the results for a 2.1-nm SiO/sub 2/ IL, it is derived that at a certain gate voltage range, electron tunneling to a defect band in the HfO/sub 2/ layer may contribute to a pronounced increase in the flicker noise.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Short-channel MOSFETs with oxynitride gate dielectrics fabricated using multiple rapid thermal processing

Short-channel MOSFETs with superior thin gate dielectrics have been successfully fabricated using multiple reactive rapid thermal processing of thermal oxides. The gate dielectrics are produced by rapid thermal nitridation (RTN) of thin thermal oxides in pure NH/sub 3/ ambient followed by rapid thermal reoxidation (RTO) in O/sub 2/ ambient. Devices fabricated with RTO/RTN gate dielectrics exhibit improved hot electron induced degradation compared to those fabricated with pure oxides. In addition, the subthreshold leakage current level of RTO/RTN devices is as good as for standard oxide devices.<>     

Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET

A detailed investigation of the negative-bias temperature instability (NBTI) of the ultrathin nitrided gate p-MOSFET over a wide temperature range reveals two different activation energies, indicating the coexistence of two distinct degradation mechanisms. One mechanism is linked to the incorporation of nitrogen while the other is the classical mechanism responsible for the degradation of conventional SiO/sub 2/ gate devices. Eliminating the contribution of the former consistently yields an Arrhenius plot that matches excellently with that obtained through direct measurement of SiO/sub 2/ gate devices. This finding shows that heavy nitridation or, in the extreme case, the adoption of Si/sub 3/N/sub 4//SiO/sub x/ gate stack does not change the nature of the classical NBTI mechanism but introduces a new degradation mechanism of an order-of-magnitude lower activation energy, which dominates over typical operating temperature range. This new mechanism is related to the spontaneous trapping of positive charges at nitrogen-related precursor sites near the Si-SiO/sub 2/ interface.     

Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.     

Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

This paper proposes a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin-film transistors, composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O plasma. The novel stack gate dielectric exhibits a very high electrical breakdown field of 8.5 MV/cm, which is approximately 3 MV/cm higher than traditional PECVD TEOS oxide. The novel stack oxide also has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics. These improvements are attributed to the formation of strong Si/spl equiv/N bonds of high quality ultra-thin oxynitride grown by PECVD N/sub 2/O plasma, and the reduction in the trap density at the oxynitride/poly-Si interface.     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances

A simple technique to form high-quality hafnium silicon oxynitride (HfSiON) by rapid thermal processing oxidation of physical vapor deposition hafnium nitride (HfN) thin films on ultrathin silicon oxide (SiO/sub 2/) or silicon oxynitride (SiON) layer is presented. Metal TaN gate electrode is also introduced into such HfSiON stacks. Excellent performances including large electron mobility (85%SiO/sub 2/at0.2 MV/cm), low leakage current (10/sup -4/ of SiO/sub 2/), and superior time-dependant dielectric breakdown reliability are achieved in HfSiON/SiO/sub 2/ stacks, and these results suggest such stacks are very promising for the low-power SOC applications in the near future. In addition, the improvement of the electron mobility in this HfSiON/SiO/sub 2/ stack by a reduction of the border traps in the HfSiON dielectric is demonstrated.     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²