Determination of interface trap capture cross sections usingthree-level charge pumping

A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO₂ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I_cp to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET     

Bulk traps in ultrathin SIMOX MOSFET's by current DLTS

Bulk traps in very thin ( ~100-nm) SIMOX films have been studied by applying current deep-level transient spectroscopy (DLTS) to fully depleted, enhancement MOS transistors, fabricated in these films. The effect of states at both the front and back SiO₂-Si interfaces is eliminated by suitable biasing. Using this technique, a bulk trap with energy level 0.44 eV above the valence-band edge, capture cross section ~10^-17 cm², and concentration ~10 ¹⁵ cm^-3, which is believed to be due to iron contamination, has been identified     

Microstructural Control of Charge Transport in Organic Blend Thin‐Film Transistors

The charge‐transport processes in organic p‐channel transistors based on the small‐molecule 2,8‐difluoro‐5,11‐bis(triethylsilylethynyl)anthradithiophene (diF‐TES ADT), the polymer poly(triarylamine)(PTAA) and blends thereof are investigated. In the case of blend films, lateral conductive atomic force microscopy in combination with energy filtered transmission electron microscopy are used to study the evolution of charge transport as a function of blends composition, allowing direct correlation of the film's elemental composition and morphology with hole transport. Low‐temperature transport measurements reveal that optimized blend devices exhibit lower temperature dependence of hole mobility than pristine PTAA devices while also providing a narrower bandgap trap distribution than pristine diF‐TES ADT devices. These combined effects increase the mean hole mobility in optimized blends to 2.4 cm²/Vs – double the value measured for best diF‐TES ADT‐only devices. The bandgap trap distribution in transistors based on different diF‐TES ADT:PTAA blend ratios are compared and the act of blending these semiconductors is seen to reduce the trap distribution width yet increase the average trap energy compared to pristine diF‐TES ADT‐based devices. Our measurements suggest that an average trap energy of <75 meV and a trap distribution of <100 meV is needed to achieve optimum hole mobility in transistors based on diF‐TES ADT:PTAA blends.     

Effects of traps on thin film transistors

Trap effects on Weimer-type thin film transistors (TFT) were studied. Measurements of thermally stimulated current (TSC), temperature dependence of drain current and MOS structure capacitance were performed to study trap distribution in TFT's. It was found that the steady state Fermi level lies near to the conduction band (0·1–0·05 eV) in the TFT. Only those traps lying near or above the Fermi level can affect the performance of TFT. Drain current relaxation effects for a step-gate voltage, and drain current hysteresis for a sine-wave gate voltage, were studied as trap effects on TFT performance. These phenomena were interpreted in terms of trap kinetics, and the roles of traps in the insulator film and in the semiconductor film were identified. The energy depth, density and cross section of traps affecting TFT performance were estimated.     

The effects of oxide traps on the MOS capacitance

The trapping of electrons and holes at a semiconductor surface by traps located in the oxide adjacent to the semiconductor has been considered. It is shown that the effective capture cross section of an oxide trap viewed by a carrier at the semiconductor surface is reduced by a factor which increases exponentially with the distance the trap is located from the interface. A pseudo-Fermi function in this position variable is developed which gives the probability that a trap will be filled (or emptied) in a measurement time, Tm. The trapping kinetics developed in the first part of the paper are applied to yield the full frequency and bias dependence of an MOS capacitor for an arbitrary spatial and energy trap distribution. Specific examples are given and the problem of voltage hysteresis is dealt with quantitatively. The conclusion is that very little information about the energy distribution and capture cross sections of the oxide traps is obtained from the analysis of MOS-capacitance curves.     

Technique for monitoring slow interface trap characteristics in MOScapacitors

A new experimental technique presented in the Letter simultaneously extracts the trap response time as well as trap density and energy in the silicon bandgap. The technique is illustrated by measuring the trap density increase in a MOS capacitor due to constant current stressing and is compared with the results obtained using the conventional quasistatic C/V technique     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Analysis of slow traps centres in submicron MOSFETs by random telegraph signal technique

In this paper, we present a comprehensive study of slow single traps, situated inside the gate oxide of small area (W×L=0.5×0.1 μm²) metal–oxide–semiconductor (MOS) transistors. The gate oxide of the analyzed transistors, which have been used for memory-cell applications, is composed of two SiO₂ layers—a deposited high-temperature oxide (HTO) and the thermal oxide. The interface between the two gate oxides is shown to play a significant role in the channel conduction: we observed that the presence of individual traps situated inside the gate oxide, at some angstroms from the interface with the channel, is inducing discrete variations in the drain current. Using random telegraph signal (RTS) analysis, for various temperatures and gate bias, we have determined the characteristics of these single traps: the energy position within the silicon bandgap, capture cross section and the position within the gate oxide.     

Effects of Fowler-Nordheim stress on interface trap density andemission cross sections in n-MOSFETs studied by three-level chargepumping

High field Fowler-Nordheim (F-N) stress effects on interface-trap density and emission cross sections in n-MOSFETs have been studied using three-level charge pumping (3LCP). The results show that 3LCP is sensitive to changes in trap cross section as a function of energy in the bandgap. An asymmetric change in electron and hole emission cross sections following F-N tunneling injection is found. The work also provides further insight into the influence of hot electrons on interface trap generation in MOSFETs in both the upper and lower bandgap following electrical stress     

Determination of bandgap narrowing and parasitic energy barriers inSiGe HBT's integrated in a bipolar technology

This paper describes a method for characterizing the bandgap narrowing and parasitic energy barrier in SiGe heterojunction bipolar transistors (HBTs), fabricated using a single-polysilicon self-aligned bipolar process. From a comprehensive study of the temperature dependence of the collector current, the bandgap narrowing in the base due to germanium has been dissociated from that due to the heavy dopant concentration. The same approach has been used to characterize the height and width of parasitic energy barriers which appear when boron out-diffusion from the SiGe base is present. The method has been applied to SiGe heterojunction bipolar transistors fabricated using a single polysilicon, self-aligned, bipolar process, as well as mesa transistors. The experimental results show that small geometry transistors have degraded collector currents due to boron out-diffusion around the perimeter of the emitter. This behavior has been explained by accelerated boron diffusion due to point defects generated during the extrinsic base implant. The values of undoped SiGe spacer thickness needed to suppress the parasitic energy barrier are described. Finally, high-frequency results are reported, which correlate the frequency transition to these parasitic energy barriers     

Anomalous off-current mechanisms in N-channel poly-Si thin film transistors

The anomalous off-current (I_off) in polysilicon thin film transistors (polysilicon TFTs) is one of the major problems preventing a wide use of these devices in active matrix liquid crystal displays. While previous investigations have focused on the temperature range above 300 K, in this study we have investigated the behaviour of I_off over a wide range of temperatures, namely 180–400 K. The data have been analysed by combining 2D simulations and existing analytic models. By this approach we have identified a pure trap-to-band tunnelling mechanism in polysilicon TFTs and deduced, by a simple procedure, the physical constants. The temperature and bias dependence of the off-current has been explained quantitatively in terms of phonon-assisted tunnelling. The number of generating centres, the dominant trap energy and the thermal capture cross section are deduced from this analysis.     

Study of the electronic trap distribution at the SiO2-Siinterface utilizing the low-frequency noise measurement

A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices with differently prepared gate oxides were used to study the process-induced trap distribution. Several peaks varying from sample to sample are found in a frequency index of noise spectrum versus temperature plot and are correlated with the discrete trap distribution across the bandgap of silicon. This method provides more information on traps as it circumvents the complexity of superimposing different traps which was encountered in the capacitance-voltage (C-V) method. Results, either compatible with others' work or consistent with data based on other measurements, show that the electronic trapping behavior in MOS structures is governed by two intrinsic traps located at 0.12 and 0.3 eV (both measured from the conduction band) for all kinds of oxides. In addition, dry oxidation was found to introduce an additional trap at an energy level of 0.23 eV, and annealing the gate oxide in ammonia at a high temperature (>1000°C) results in an enhancement of the trap density of 0.43 eV below the conduction band edge of silicon, which was also observed in a quasi-static C-V measurement     

Theory of non-steady-state interfacial thermal currents in MOS devices,and the direct determination of interfacial trap parameters

Generalized equations are derived that permit the determination of the non-steady-state, thermal current vs temperature characteristics due to the emission of charge from interface states in MOS devices when the temperature increases uniformly with time. The equations are applicable to any trap distribution that extends over more than about 4kT in energy; the equations for discrete traps are also presented.The important result emerging from this work is that in the case of distributed traps the I?T characteristic is a direct reflection of the energy distribution of the interface traps. Furthermore, it is shown how the attempt-to-escape frequency ν of the traps and, hence, their capture cross-section may be determined. The determination of the trap density and energy and ν for discrete trap levels is also discussed.     

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10^?6/°C when temperature is changed from ?40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of ?104.54 dB, ?104.54 dB, ?104.5 dB, ?101.82 dB and ?79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.     

Light sensitivity of current DLTS and its implications on the physics of DC-to-RF-dispersion in AlGaAs-GaAs HFETs

The light sensitivity of current deep-level transient spectroscopy (I-DLTS) is analyzed with the aim of gaining insight about the physics of surface-trap related dc-to-RF dispersion effects in AlGaAs-GaAs heterostructure field-effect transistors. I-DLTS experiments under dark reveals three surface-trap levels with activation energies 0.44 eV (h1), 0.59 eV (h2), and 0.85 eV (h3), as well as a bulk trap with activation energy 0.45 eV (e1). While the I-DLTS signal peaks associated with the two shallower surface traps h1 and h2 are suppressed by optical illumination with energy larger than the AlGaAs bandgap, that which is associated with the deepest surface trap h3 is nearly unaffected by light up to the highest intensity adopted. Two-dimensional device simulations assuming that surface traps behave as hole traps provide an interpretation for the observed different light sensitivity of surface traps, explaining it as the result of the temperature dependence of surface hole concentration and negative trap-charge density, making trap-charge modulation at increasing temperature less and less sensitive to excess carriers generated by light.     

An analytical model to project MOS transistor lifetime improvement by deuterium passivation of interface traps

Based on the hydrogen/deuterium (H/D) isotope effect in interface trap generation and the power law that is widely used to describe the hot-carrier degradation of MOS transistors, a universal model is developed to project the hot-carrier lifetime improvement of MOS transistors by deuterium (D) passivation of interface traps. The validity of this model is verified by comparing its predication with the experimental measurements. The result indicates that the lifetime improvement increases more than exponentially as the D passivation fraction increases.     

Interface states in SiSiO2 interfaces

Interface state parameters were studied in MOS capacitors over a wide range of energy by conductance and capacitance measurements at various temperatures from room temperature to liquid nitrogen temperature. A new technique was developed for analysis of the data which allows to obtain the density of states, the capture cross section, the surface potential and the dispersion parameter from the conductance and capacitance vs. frequency curves. The density of interface states as well as the electron capture cross section were found to be a function of energy only and to be independent of temperature. Maxima in the density of states have not been found.     

Three level charge pumping on a single interface trap

We present results obtained by performing two and three level charge pumping (CP) technique on a single trap present at the SiO₂ /Si interface of deep-submicron MOS transistor (50 nm length). Using two-level CP method, we have measured the emission time constant of a single trap and we have verified by numerical simulations the Shockley-Read-Hall (SRH) theory. Three level CP measurements allow an accurate determination of the capture cross section and the energy level of the trap. For the particular trap presented in this paper, we have found E_t - E_V ≈ 0.83 eV, σ_n ≈ 6 × 10^-17 cm²     

Interfacial electronic traps in surface controlled transistors

Carrier recombination at interfacial electronic traps under a surface controlling gate electrode is analyzed using the Shockley-Reed-Hall steady-state recombination kinetics to provide a theoretical basis for quantifying the direct-current current-voltage (DCIV) method for monitoring and diagnosis of MOS transistor reliability, design, and manufacturing processes. Analytical expressions for DCIV lineshape, linewidth, peak gate-voltage and peak amplitude are derived for the determination of interface trap densities, energy level, and spatial location. DCIV peaks in the intrinsic to flat band gate-voltage range originate from carrier recombination at interface traps located over the channel region. Additional peaks in the surface accumulation gate-voltage range originate from interface traps covering the gated p-n-junction space-charge region. Effects on the DCIV line shape from minority carrier injection level and diffusion are described. Examples are given for the determination of the quantum density of states of process-residual interface traps of unstressed MOS transistors as well as hot-carrier-generated interface traps of stressed MOS transistors     

Non-ideal base current in bipolar transistors at low temperatures

Bipolar transistors havetraditionally been considered not useful in low-temperature applications. This assumption, however, is based upon an incomplete physical understanding of bipolar device physics at low temperatures. This paper shows experimentally that recombination mechanisms play a substantially larger role in determining base current at low temperatures than at room temperature. The results are explained and quantitatively modeled using conventional Shockley-Read-Hall theory, with the addition of the Poole-Frenkel high field effect. It is concluded that trap levels in the silicon bandgap due to bulk traps or interface states are very important in determining bipolar transistor base currents at low temperatures. Non-ideality factors larger than 2 are often observed. Such trap levels will have to be carefully controlled if low-temperature operation of bipolar transistors is to be considered.