Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

High-Speed Digital IC Performance Outlook

This paper, which is a tutorial on high-speed GaAs digital IC's, was given as one of the 1984-1985 MTT-S Distinguished Microwave Lectures. It reviews GaAs FET technology and issues related to device/ circuit design and fabrication of digital circnits of MSI/LSI complexity operating at gigahertz clock frequencies; discusses limitations of the technology; compares GaAs technology with competing Si bipolar transistors, GaAIAs HEMT, and GaAIAs HBT technologies and projects performance of GaAs digital IC technology in applications where it will have a significant impact on microwave systems.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology

The successful development of a new integrated circuit (IC) technology requires a significant effort in process evaluation. This is particularly true for the high-speed low-power planar GaAs digital IC technology, which involves a relatively new semiconductor material, new processing techniques, and pursues LSI complexity using very-fine-line lithography (1-µm dimensions). This paper contains a review of the strategy employed to monitor and evaluate each of the key process steps, and to evaluate the uniformity of device parameters. The principal process evaluation test structures are discussed along with measurement techniques, and examples of measurement results are given. Our emphasis on measurement automation to facilitate the collection of a large volume of data and their statistical analysis is reflected in the paper. Examples of wafer statistics are given.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

GaAs digital IC technology/statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.     

GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

GaAs MESFET ICs for gigabit logic applications

This paper gives an overview of the basic concepts used in the design and fabrication of gallium arsenide MESFET integrated circuits intended for gigabit logic applications. The present status of speed-power performances, packing densities, and integration levels is presented on the basis of some MSI and LSI MESFET IC realizations made possible by the principal GaAs logic approaches to date. Finally, the potential field of application and future trends of GaAs IC technology are assessed.     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

TiW Silicide gate self-alignment technology for ultra-high-speed GaAs MESFET LSI/VLSI's

It has been found that TiW silicide film forms Schottky contacts on GaAs which are extremely stable even at temperatures of up to 850°C. Using this silicide for gate material, a novel self-alignment technique for GaAs MESFET's has been developed. A minimum propagation delay of 50 ps with 1.5-µ gate logic and successful fabrication of 1-kbit fixed address GaAs static memory cell arrays which are based on E/D type DCFL's indicate that TiW silicide gate self-alignment technology is a very promising candidate for achieving ultra-high-speed GaAs MESFET LSI/VLSI's.     

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I²L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I²L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I²L and STL device designs. Power-delay products of 14 fJ for I²L and 30 fJ for STL have been measured.     

A 150-MOPS GaAs 8-bit slice processor

The architecture, circuit design, and test results for a GaAs 8-b slice processor IC are presented. The device is a high-speed cascadable element intended for use in MIL-STD-1750A computers, reduced-instruction-set computer (RISC) systems, signal processors, and numerous other applications where high speed and radiation hardness are required. The bus-oriented architecture features a 31-word×8-b two-port register file, a fast eight-function ALU, an 8-bit address port an 8-b bidirectional data port, and associated shifting, decoding, and multiplexing functions. Ancillary logic commonly mechanized in external hardware has been included on-chip. The 9400-transistor LSI device demonstrated peak performance above 150 million operations per second (MOPS) at 9.2 W; a lower power version executes 100 MOPS at 4.2 W     

A gigabit-rate five-highway GaAs OE-LSI chipset for high-speedoptical interconnections between modules or VLSIs

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GsAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit     

High speed GaAs integrated circuits

Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.