高功率二极管激光器Au80Sn20焊料焊接实验研究

半导体激光器封装工艺过程对于激光器的输出特性、寿命等性能有重要影响,其中焊料的选择和焊接工艺是最关键的因素。本文采用磁控溅射的方法,在 WCu 热沉上制备了Au80Sn20合金焊料,取代了传统的In焊料,并对焊接工艺进行了改进。国外沉积的和我们制备的Au80Sn20合金焊料焊接DL芯片后的性能参数很接近。充分说明双靶分层溅射镀膜可以实现二极管激光器的封装要求,从而为优化半导体激光器制备工艺和提高半导体激光器的性能奠定基础。     

电镜原位电子束辐照下Au85 Sn15纳米线的动态熔化过程（英文）

金锡合金焊料由于其良好的性能逐渐成为一种可能替代锡铅焊料的无铅焊料,并且利用电子束辐照的焊接方式,一维金锡纳米线已经成功用于TiO_2纳米线的焊接,这为钛基半导体氧化物纳米材料的焊接提供了实验经验。然而,金锡焊料在电子束焊接时的熔化机制和动态过程的研究还很贫乏。在本文中,我们通过电化学沉积的方法制备了一维Au₈₅ Sn₁₅合金纳米焊料,并详细地研究了在透射电镜中的电子束辐照下,其形貌,晶体结构,化学元素分布的演化过程,并进一步探究了电子束辐照熔化纳米焊料的机理。研究发现,在电子束辐照下,一维Au₈₅ Sn₁₅合金纳米焊料的形貌由线状熔化为液滴状;其晶体结构由AuSn和Au_5 Sn为主,少量Au,β-Sn,SnO_2的混合相转化为单一的Au_5 Sn相;其化学元素在电子束辐照下发生质量损失,该过程既有物理相变又有化学相变。在电子束辐照传递的能量作用下,原子的流动或扩散迁移和重新排列是形成新的结合层的动力学机制。该工作不仅为应用纳米焊料进行电子束焊接提供了实验依据,而且为电子束辐照熔化金锡纳米合金纳米焊料的内在机制的研究提供了宝贵经验。     

激光器芯片烧结用AuSn薄膜焊料制造技术研究

共晶成分的金锡合金焊料AuSn20,具有较高的热导率、剪切强度、抗热疲劳性和抗腐蚀性,在高功率电子器件和光电子器件封装中应用广泛。本文在AlN陶瓷基板上,通过分层电镀Au/Sn/Au三层薄膜并合金化的方法,在AlN陶瓷表面制备了一种预制AuSn20合金焊料的基板。分析了焊料的成分及性能,结果满足国军标GJB 548B-2005 《微电子器件试验方法和程序》的剪切强度要求。用该基板封装激光二极管后达到设计功率,光功率效率为35%。     

电化学制备金锡合金薄膜技术研究

共晶成分的金锡合金具有诸多优异性能,文章介绍了一种制备金锡合金的方法,采用该方法在陶瓷基体上面制备金锡薄膜焊料.对焊料的成分进行了检测,对焊料的焊接性能和焊接可靠性进行了测试.试验结果满足GJB548相关要求.     

微波GaAs功率芯片的低空洞率真空焊接技术研究

文章选用80Au20Sn焊料对微波GaAs功率芯片的焊接技术进行了较为系统深入的研究,通过对共晶焊接设备与真空烧结设备分别对焊接时气体保护、焊片大小、真空工艺过程的施加和夹具设计等因素进行了试验分析。结果表明,以上参数对微波GaAs功率芯片焊接均有显著的影响,在保护气体流量为1.5L·min^-1的氮气保护下,通过施加适当的夹具静压力和金锡焊料熔化时的抽真空应用,AuSn焊料能够充分和快速润湿,实现较高的焊接质量。X射线检测结果表明,微波GaAs功率芯片焊接具有较低的空洞率,焊透率高达90％以上,焊接过程主要通过夹具装配完成,人为影响因素少,成品率高。     

大功率半导体激光器高可靠烧结技术研究

近几年大功率半导体激光器的应用领域越来越广,许多应用领域都要求半导体激光器能够高可靠性工作.工作焊接质量直接影响着大功率半导体激光器的可靠性,焊接缺陷会导致激光器迅速退化.目前国内普遍采用的铟焊料和锡铅焊料都是软焊料,焊层有形成晶须和热疲劳等可靠性问题.为提高烧结可靠性,采用了金锡焊料烧结激光器新技术.金锡焊料是硬焊料,焊接强度高,抗疲劳性好,对金层无浸蚀现象.通过实验研究掌握了金锡焊料的制备和烧结技术,并与铟焊料、锡铅焊料进行了对比实验.实验结果显示采用金锡焊料烧结激光器可获得更好的性能,是提高半导体激光器可靠性的有效途径.     

Sn95Sb5焊料与ENIG/ENEPIG镀层焊点界面可靠性研究

研究了Sn95Sb5焊料在化学镍金(ENIG)镀层、化学镍钯浸金(ENEPIG)镀层表面形成的焊点界面微观组织形貌与剪切强度。使用Sn95Sb5焊料在FR4印制板上焊接0805片式电容,焊点在高温时效测试和温度循环过程中均表现出较高的剪切强度,焊点界面连续且完整,剪切强度下降的最大幅度不超过19.2%。Sn95Sb5焊料在ENIG镀层表面形成的焊点(Sn95Sb5/ENIG焊点)强度更高。Sn95Sb5焊料在ENEPIG镀层表面形成的焊点(Sn95Sb5/ENEPIG焊点)界面反应更为复杂,在焊点界面附近可观察到条块状的(Pd,Ni,Au) Sn₄。Sn95Sb5/ENEPIG焊点界面的金属间化合物层平均厚度约为Sn95Sb5/ENIG焊点界面的2倍。     

钢/镁异种金属搭接添加Sn箔激光熔焊接头的微观组织分析

采用光纤激光器作为焊接热源的激光熔焊工艺对双相钢DP600和变形镁合金AZ31进行添加Sn箔的搭接焊研究。通过调整焊接参数获得最佳焊接成形,采用卧式金相显微镜、带有能谱仪(EDS)和电子背散射衍射(EBSD)探头的扫描电镜(SEM)和X射线衍射仪(XRD)等观察焊接接头的微观组织、相分布、晶粒大小、元素分布和相结构组成。结果表明,添加Sn箔激光熔焊是一种适用于Fe和Mg异种材料连接的有效方法,通过过渡区域形成新相可实现Mg/Fe有效连接。实验还发现,钢上、镁下搭接激光熔焊上层双相钢的热影响区未出现明显的软化组织,焊接熔池和钢/镁接头过渡区域未见大规模氧化物和气孔缺陷,钢侧过渡区域生成Fe Sn、Fe1.3Sn、Fe3Sn等Fe-Sn相,镁侧过渡区域生成柱状枝晶的Mg2Sn相,这些新相的存在可实现钢/镁异种金属的"双向"冶金结合。     

含Ni膜系耐铅锡焊料焊接的特性研究与验证

微波集成电路中传统的NiCr—Au膜层和Sn63Pb37焊料焊接时，Au在高温下易和熔融Sn63Pb37焊料反应生成脆性的AuSn2甚至AuSn4，带来焊接和长期工作的可靠性等问题。本文针对这种现象，从焊料和膜层两个方向展开研究，对微波集成电路的常规膜系提出了一种改进方案，并进行一系列验证试验。     

超大面积芯片烧结技术研究

随着半导体大功率器件的发展,芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导,芯片焊接工艺是直接影响器件散热好坏的关键因素之一,合金焊料的一个显著优点就是其导热性能好,因此在散热要求高的大功率器件中使用较为广泛(如Au80Sn20、Au99.4Sb0.6等),但由于合金焊料烧结后会产生较大的残余应力,在尺寸大于8 mm×8 mm的芯片上,烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验,经过对应力产生的原因进行分析,从材料、封装工艺等方面采取措施来降低缓释应力,并对封装产品进行可靠性考核验证。试验结果表明,没有芯片存在裂纹、碎裂现象,产品通过了可靠性验证。     

Study of wetting reaction between eutectic AuSn and Au foil

Wetting reactions between eutectic AuSn solder and Au foil have been studied. During the reflow process, Au foil dissolution occurred at the interface of AuSn/Au, which increases with temperature and time. The activation energy for Au dissolution in molten AuSn solder is determined to be 41.7 kJ/mol. Au₅Sn is the dominant interfacial compound phase formed at the interface. The activation energy for the growth of the interfacial Au₅Sn phase layer is 54.3 kJ/mol over the temperature range 360–440°C. The best wettability of molten AuSn solder balls on Au foils occurred at 390°C (wetting angle is about 25°). Above 390°C, the higher solder oxidation rate retarded the wetting of the molten AuSn solder.     

Study of wetting reaction between eutectic AuSn and Au foil

Wetting reactions between eutectic AuSn solder and Au foil have been studied. During the reflow process, Au foil dissolution occurred at the interface of AuSn/Au, which increases with temperature and time. The activation energy for Au dissolution in molten AuSn solder is determined to be 41.7 kJ/mol. Au₅Sn is the dominant interfacial compound phase formed at the interface. The activation energy for the growth of interfacial Au₅Sn phase layer is obtained to be 54.3 kJ/mol over the temperature range 360–440°C. The best wettability of molten AuSn solder balls on Au foils occurred at 390°C (wetting angle is about 25°). Above 390°C, the higher solder oxidation rate retarded the wetting of the molten AuSn solder.     

进口AuSn20焊料环特性及焊缝化合物分析

AuSn20焊料环是高可靠密封工艺中一种常用的密封材料,采用差示扫描量热法对进口AuSn20焊料环进行熔化和凝固温度的检测,探明其熔化温度为280℃,凝固温度为277℃,AuSn20焊料环纯度很高几乎无杂质.通过对进口和国产AuSn20焊料环的表面状态形貌进行对比,发现均为AuSn和Au5Sn的均匀分布状态,未见明显区...     

Characterization of 63Sn37Pb and 80Au2OSn solder sealed opticalfiber feedthroughs subjected to repetitive thermal cycling

A highly accurate prediction of hermeticity lifetime is made for eutectic 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber-Kovar ^TM nosetube feedthroughs subjected to repetitive thermal cycling. Thermal fatigue fracture of the Sn-Pb solder/Kovar^TM interface develops when cracks, initially generated from creep deformation of the solder, propagate gradually through the junction in the axial direction. A nonlinear axisymmetric finite element analysis of the 63Sn37Pb fiber feedthrough seal is performed using a thermo-elastic creep constitutive equation, and solder joint fatigue based on accumulated strain energy associated with solder creep imposed by temperature cycling is analyzed. Additionally, thermal effective stress and plastic strain is studied for alternative 80Au20Sn solder by the finite element method with results indicating significant increase in useful life as compared to 63Sn37Pb. SEM/EDX metallurgical analysis of the solder/Ni-Au plated Kovar^TM nosetube interface indicates that AuSn₄ intermetallic formed during soldering with 63Sn37Pb also contributes to joint weakening, whereas no brittle intermetallic is observed for 80Au20Sn. Hermetic carbon coated optical fibers metallized with Ni,P-Ni underplate and electrolytic Au overplating exhibit correspondingly similar metallurgy at the solder/fiber interface. Combined hermeticity testing and metallurgical analysis carried out on 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber feedthroughs after repetitive temperature cycling between -65 and +150°C, and -40 and +125°C validated the analytical approach     

Fluxless Flip-Chip Solder Joint Fabrication Using Electroplated Sn-Rich Sn–Au Structures

A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn–Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn–Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn–Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au$_5$Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217$^circ$C–222$^circ$C. The plated Sn–Au solder bumps on silicon with 50$mu$m in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited.     

Modified Face-Down Bonding of Ridge-Waveguide Lasers Using Hard Solder

A modified face-down bonding technique of ridge-waveguide laser diodes (LDs) using 80Au20Sn solder has been performed. For ease of manufacturability, a bonding window with good bonding integrity and improved optical performance was determined. Metallographical investigation showed that the solder joint comprised of a layer of delta phase compound near the solder/heatsink interface, a layer of (Au,Ni)Sn intermetallic compound (IMC) at the solder/heatsink interface, and zeta' phase Au/Sn compound at the center of the solder joint. The delta phase shifted to the interfaces after reflow was postulated by its lower surface tension than zeta' phase Au/Sn compound. Good bonding integrity was observed with LD residues still adhering onto the bond pad after die shear testing. Scanning electron microscopy (SEM)/energy dispersive X-ray (EDX) analyses of the fracture surface showed that the fracture occurred within the LD, at the GaAs/SiN interface. LDs bonded with this modified bonding process achieved an optical improvement of 2.5-3X compared to the unbonded LDs due to its good thermal management. These bonded LDs further exhibited good long-term reliability with no significant degradation in optical performance and no significant microstructure evolution in the solder joint after 500 thermal cycling test.     

Mechanical reliability of Sn-rich Au–Sn/Ni flip chip solder joints fabricated by sequential electroplating method

In this study, we evaluated the mechanical reliability of Sn-rich, Au–Sn/Ni flip chip solder bumps by using a sequential electroplating method with Sn and Au. After reflowing, the average diameter of the solder bump was approximately 80 μm and only a (Ni,Au)₃Sn₄ intermetallic compound (IMC) layer was formed at the interface. Due to the preferential consumption of Sn atoms within the solder matrix during aging, the solder matrix was transformed sequentially in the following order: β-Sn and η-phase, η-phase, and η-phase and ε-phase. In the bump shear test, the shear force was not significantly changed despite aging at 150 °C for 1000 h and most of the fractures occurred at the interfaces. The interfacial fracture was significantly related to the formation of brittle IMCs at the interface. The Sn-rich, Au–Sn/Ni flip chip joint was mechanically much weaker than the Au-rich, Au–Sn/Ni flip chip joint. The study results demonstrated that the combination of Sn-rich, Au–Sn solder and Ni under bump metallization (UBM) is not a viable option for the replacement of the conventional, Au-rich, Au–20Sn solder.     

Microstructure of eutectic 80Au/20Sn solder joint in laser diode package

Laser diodes (LD) are usually bonded onto heat sinks for the purposes of heat dissipation, mechanical support and electrical interconnect. In this study, energy dispersive X-ray analysis (EDX) and electron backscatter diffraction (EBSD) are employed to investigate the microstructure evolution of 80Au/20Sn solder joint in LD package. During reflow, Pt-Sn and (Au, Ni)Sn IMCs were formed at the respective LD/solder and solder/heatsink interfaces, while δ, β and ζ′ phases of Au/Sn intermetallics were found in the solder joint. The Au-rich β and ζ′ phases in the solder joint limit the growth of interfacial IMCs. Chip shear testing showed that the failure occurred within the LD, with partial brittle fracture at the GaAs substrate and partial interfacial delamination at the GaAs/SiN interface. The strong solder bond can be attributed to the high mechanical strength of 80Au/20Sn solder, which provides improved stability for high temperature applications.     

Microstructure evolution of gold-tin eutectic solder on Cu and Ni substrates

The microstructures of the eutectic Au20Sn (wt.%) solder that developed on the Cu and Ni substrates were studied. The Sn/Au/Ni sandwich structure (2.5/3.75/2 μm) and the Sn/Au/Ni sandwich structure (1.83/2.74/5.8 μm) were deposited on Si wafers first. The overall composition of the Au and the Sn layers in these sandwich structures corresponded to the Au20Sn binary eutectic. The microstructures of the Au20Sn solder on the Cu and Ni substrates could be controlled by using different bonding conditions. When the bonding condition was 290°C for 2 min, the microstructure of Au20Sn/Cu and Au20Sn/Ni was a two-phase (Au₅Sn and AuSn) eutectic microstructure. When the bonding condition was 240°C for 2 min, the AuSn/Au₅Sn/Cu and AuSn/Au₅Sn/Ni diffusion couples were subjected to aging at 240°C. The thermal stability of Au20Sn/Ni was better than that of Au20Sn/Cu. Moreover, less Ni was consumed compared to that of Cu. This indicates that Ni is a more effective diffusion barrier material for the Au20Sn solder.