Delta Sigma调制器非理想因素建模

系统构建并研究了开关电容积分器DeltaSigma调制器非理想因素行为级模型.重点实现一种运放非线性直流增益模型,仿真表明它更有效反映奇次谐波失真,为保证模型真实性,综合考虑调制器其他非理想因素,如时钟抖动、量化器失配、采样噪声、开关非线性电阻以及运放参数(色化噪声、饱和电压、增益带宽、摆率等).     

The MOS capacitor amplifier

It is well known that low noise amplification can be performed by using a capacitor whose capacitance can be controlled. In this paper, it is shown that changing the inversion level of a MOS transistor allows voltage amplification. The theoretical characterization of this amplifier in terms of gain and harmonic distortion is made, and comparisons with HSPICE results are performed. Finally, some practical considerations to improve the performance of the circuit are presented.     

1.2-V CMOS op-amp with a dynamically biased output stage

A very low-voltage operational amplifier in a standard CMOS process with a 0.75 V threshold voltage is presented. It uses a novel dynamically biased output stage based on the switched-capacitor approach. Thanks to this, drive performance is greatly improved and accurate current control is also achieved. The amplifier is capable of working with a power supply as low as 1.2 V while providing a -74 dB total harmonic distortion with a 700 mV peak-to-peak output voltage into a 500 Ω and 20 pF output load. The open-loop gain and the gain-bandwidth product are higher than 90 dB and 2.2 MHz, respectively     

A low power and low distortion rail-to-rail input/output amplifier using constant current technique

A rail-to-rail amplifier with constant transconductance,intended for audio processing,is presented.The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region.MOSFETs working in the weak inversion region have the advantages of low power and low distortion.The proposed rail-to-rail amplifier,fabricated in a standard 0.35μm CMOS process,occupies a core die area of 75×183μm~2.Measured results show that the maximum power consumption is 85.37μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2%at 2 kHz.     

一种低压、恒增益Rail-to-rail运算放大器的设计

文章设计了一种低压、恒定增益、Rail-to-rail的CMOS运算放大器。该放大器采用直接交迭工作区的互补并联输入对作为输入级,在2V单电源下,负载电容为25pF时,静态功耗为0.9mW,直流开环增益、单位增益带宽、相位裕度分别为74dB、2.7MHz、60°。     

防破音D类音频功放的设计与应用

随着多媒体便携设备的普及,音频功放已经成为音频部分的标准配置,D类功放以其高品质高效的特点得到了越来越广泛的应用。在便携产品中,音频功放由于输入音乐信号过大或者电源电压过低,会产生削顶失真。采用防破音技术,可以通过自动增益调节技术来提供一个完美的解决方案。文章介绍了常见的防破音技术,提出了一种改进的AGC(自动增益控制)技术在D类功放中的设计与应用。改进的AGC技术通过对PWM输出的采样来判断失真程度,依据失真程度用防破音电路产生的PWM波形来自动调节运放增益,实现最大功率的无失真输出。     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

Low power LNA using the MOSFETs in moderate inversion

This paper presents an integrated complementary metal oxide semiconductor (CMOS) low power low noise amplifier (LNA) for global positioning system (GPS) receivers.To achieve low power dissipation,the MOS transistors in the proposed LNA are biased in moderate inversion region.It is implemented by SMIC 180 nm 1P6M CMOS process.The experiment results show that a gain of 12.14 dB@1.57 GHz is achieved with low noise figure (NF) of 1.62 dB.The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V.The ratio of gain to dc power consumption is 8 dB/mW.The size of the LNA is only 980μm× 720μm including the pads.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Using the weak inversion region to optimize input stage design of CMOS op amps

Operation of MOS devices in the strong, moderate, and weak inversion regions is considered. The advantages of designing the input differential stage of a CMOS op amp to operate in the weak or moderate inversion region are presented. These advantages include higher voltage gain, less distortion, and ease of compensation. Specific design guidelines are presented to optimize amplifier performance. Simulations that demonstrate the expected improvements are given.     

高输出电压的宽带程控增益放大系统

设计了以电压控制可变增益放大器AD603为程控增益主体,以MSP430F449单片机为控制核心的高电压输出宽带程控增益放大系统.系统电压增益为0～60 dB可调,3 dB带宽2.5 MHz、5 MHz、10 MHz、15 MHz可调,最小输入电压有效值为1 mV,在50 Ω负载下最大不失真输出电压峰峰值为28 V,电压...     

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

宽带碲基掺铒光纤放大器上能级粒子数反转比

对宽带碲基掺铒光纤放大器(EDTFA)上能级粒子数反转比进行了理论研究,得到了碲基掺铒光纤放大器上能级粒子数反转比随着光纤激活长度、信号输入功率、泵浦功率和纤芯掺杂浓度的演变关系,分析了上能级粒子数反转比分布与EDTFA信号增益间的关系.研究表明,碲基掺铒光纤内的上能级粒子数反转比分布决定了EDTFA的信号增益.     

A wide-band operational amplifier with a new output stage and a simple frequency compensation

Innovations in circuit design have resulted in a high-performance wide band operational amplifier made by standard integrated-circuit production processes. A new class-B output circuit with very low distortion and high quiescent current stability a coupling method for differential amplifier stages incorporating the elimination of amplifier stages at high frequencies to obtain a first-order frequency response and an input stage combined with a level shift with lateral p-n-p transistors having capacitive feed forward to increase the bandwidth are used in this amplifier. A unity gain bandwidth of 50 MHz with an open-loop voltage gain of 3.10/SUP 5/ and an input bias current of 10 nA are obtained.     

一种高传真电子管扩音机的设计

为解决以往的电子管扩音机倒相级存在屏阴分割倒相电路无电压增益、上下两臂输出阻抗不等、上下两臂对地分布电容不等等问题,设计了一种高传真扩音机。该扩音机采用将前置放大电子管的信号输入倒相管的"信号地"电位抬至与第倒相管的阴极相等的电路,解决了传统屏阴分割倒相电路的上述问题,并采用合理的设计改善了扩音机的谐波失真与频率特性。     

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.     

基于MSP430的直流宽带放大器设计

以压控增益宽带放大器VCA810为主,配合低噪声高速运放OPA820ID和高输出电压低失真运放THS3091D,设计并制作一个基于超低功耗单片机MSP430F155的5 V单电源供电的宽带低噪声放大器。由单片机软件实现VCA810增益控制及输出波形幅值显示。电压增益为-20~＋60 dB可调,在最大增益下,通频带为10 Hz~10 MHz,负载50Ω情况下可输出峰峰值29 V的电压。为解决宽带放大器的自激问题及减小输出噪声,采用了多种形式的抗干扰措施,抑制噪声,改善放大器的稳定性。     

一种适用于微传感器读出电路的低噪声、低失调斩波放大器

提出一种适合微传感器读出电路的高精度折叠共源共栅放大器.基于斩波技术和动态元件匹配技术,降低了折叠共源共栅放大器的噪声和失调,采用低阻节点斩波的方法和低压共源共栅电流镜扩大了放大器可处理的输入信号带宽和输出电压摆幅.芯片在0.35μm 2P4M CMOS工艺下设计并流片,测试表明在3.3V的典型电源电压和100kHz的斩波频率下,斩波放大器具有小于93.7μV的输入等效失调电压典型值,19.6nV/Hz的输入等效噪声,开环增益达83.9dB,单位增益带宽为10MHz.     

A wide-band ultralinear amplifier from 3 to 300 MHz

The design of a low-distortion, wide-band amplifier with 75-/spl Omega/ input and output impedances is described. Simultaneous shunt and series feedback is used and design equations are derived for terminal impedances, forward gain, loop gain, and noise figure. The advantages of a Darlington connection for low distortion are described. For 0-dBm signal levels, the amplifier achieves third-order intermodulation products of -88 dB relative to the carrier at 300 MHz and 12 channel cross-modulation (CM) of -77 dB at channel 13.     

A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain

A fully differential operational amplifier has been designed and fabricated for a novel high resolution and high frequency analog-to-digital converter(>12-bit). The amplifier mainly consists of folded cascode structure with current source as output loads and common-mode feedback circuits. The technique of feedforward compensation is used in order to improve the settling time and gain bandwidth (GBW) of this amplifier. This amplifier is integrated in 0.8 mm BiCMOS process with an active die area of 0.1 mm². The DC gain of this amplifier is 90 dB. The GBW and phase margin of this amplifier is 900 MHz and 47°, respectively. The power dissipation is minimized by using BiCMOS technology and is about 25 mW for 2 pF load capacitance. This level of performance is competitive with CMOS and BiCMOS operational amplifier circuits previously reported by nearly two orders of magnitude.Ecole Polytechnique of the University of Montreal