An epitaxially-grown charge modulation device

A charge modulation device (CMD) has been fabricated in a p-type epitaxial layer grown from the buried-channel silicon region of a charge-coupled device (CCD). Construction of the CMD directly above the CCD buried-channel and over the oxidized CCD transfer gates lowers the effective sense capacitance while providing isolation of the CMD source/drain regions. Responsivity values of 28 and 66 μV/e for feedback and no feedback conditions, respectively, were measured dynamically on test devices. Input-referred noise values of approximately four electrons r.m.s. were calculated from noise spectral density measurements assuming a low-pass filter 3 dB cutoff frequency of 5 MHz and correlated double sampling     

Analysis of operational speed and scaling down the pixel size of acharge modulation device (CMD) image sensor

In a previous paper, the authors (ibid., vol.38, pp.989-998, May 1991) clarified the operational mechanism of a charge modulation device (CMD) image sensor and confirmed that numerical calculations using the transistor analysis program for imagers calculating non-steady-state equations (TRINE) predicted the actual performance of a CMD imager within a 20% discrepancy. Following these results, the scaling-down of device dimensions and the inherent operational speed are estimated using TRINE in order to realize a future high-resolution CMD image sensor. The analysis shows that a device size of 5.0 μm (H)×5.2 μm (V) is attainable without degrading the performance of the 10.2 μm (H)×10.4 μm (V) CMD imager and that the operational speed of a CMD is fast enough for a high-definition TV (HDTV) application which requires a scan rate of several tens of nanoseconds     

Ideal mode operation of an InSb charge injection device

Unlike Si or HgCdTe CID (charge injection device) arrays, which normally operate at ∼1 MHz with the presence of a ≲ 10 percent fat zero (i.e., ideal mode), current InSb CID arrays fabricated on InSb substrates can operate either at a much lower clock frequency of ∼ 10 kHz (i.e., slow charge transfer mode), or when both row and column potential wells are partially filled with a large bias charge (i.e., charge sharing mode). The slow charge transfer mode is very ineffective in reading out signal charge from a large-area array and the charge sharing mode exhibits difficulties such as reduced readout efficiency, increased line capacitance, and a large photocurrent effect. By contrast, the ideal mode is free of these problems. In this paper we describe the design and fabrication of an InSb CID array, which for the first time, successfully demonstrates the ideal mode operation.     

A matched filter using charge coupled device for pulse-code modulation

A matched filter using CCD for PCM is made. The experimental results of output waveform, transfer function and output signal-to-noise ratio are given and compared with the theoretical ones. The output signal-to-noise ratio for the non-return-to-zero codes is 1 dB below the theoretical value.     

Mathematical modeling of semiconductor-on-insulator (SOI) device operation

Numerical modeling of SOI devices is proposed through use of a bipolar carrier and time-dependent approach. Poisson's equation and the current continuity equations for electrons and holes are solved simultaneously. The former is solved over the whole area of the device in question, and the electrostatic potential at the silicon-insulator interface is determined so as to fulfill Gauss's theorem. To achieve accurate numerical calculations and to obtain a stable convergence in the numerical scheme, a variable transformation is employed in the current continuity equation. That is, quasi-Fermi potentials for electrons and holes rather than carrier densities are directly analyzed. An insulated layer is modeled in the current continuity equation using the zero intrinsic-carrier density and zero mobility to realize zero conductance in an insulator. Sample calculations demonstrate a quick and stable convergence in the numerical scheme, and clarify the operational mechanism of SOI devices. This modeling should become a helpful aid in SOI device design.     

Optoelectronic charge coupled device (OECCD) using InP MIScapacitor array

An optoelectronic charge coupled device (OECCD) which is directly compatible with an incident optical signal is proposed. The nonlinear partial differential equation consisting of optical generation and recombination is solved in one dimension using the Crank-Nicolson finite-difference scheme. The charge transfer inefficiency is the main parameter considered for the calculation     

Small-Size Complex Microwave Devices (CMD) for Onboard Applications

Small-size complex microwave devices (CMD) are designed for applications in onboard air-, sea-, and ground-based radio-electronic systems. They are compact integrated multifunctional devices, which are capable of providing generation, processing, and amplification of complex multifrequency microwave signals, although their operating frequency band is relatively low - about 2%. Small-sized and miniature multiple-beam klystrons are, as a rule, the output power tube of choice for onboard CMDs. CMDs are usually applied to systems where high power, high level of integration (multifunctionality), and high signal quality are desired. Design parameters and performance capability for several onboard CMDs are discussed in this paper. In addition, distinctions between onboard CMDs and state-of-the-art onboard microwave power modules are considered     

High-temperature charge loss mechanism in a floating-gate EPROMwith an oxide-nitride-oxide (ONO) interpoly stacked dielectric

The intrinsic charge loss rate of a floating-gate EPROM cell at temperatures above 300°C appears to be much higher than the prediction from the authors' previous model (1990) developed at lower temperatures. A detailed study of intrinsic charge loss rate at temperatures ranging from 340 to 430°C reveals that it follows a Frenkel-Poole model with a barrier height of 1.9 eV. The physical origin of this high-temperature charge loss is proposed. The model suggests that electrons leak through the thin bottom poly oxide and nitride, and then thermally surmount the barrier at the nitride/top-oxide interface     

Fabrication and operation of a velocity modulation transistor

The velocity modulation transistor (VMT) has two channels with differing velocities. Small vertical distances between these channels can be achieved using epitaxial growth, opening the opportunity for higher speed than the high electron mobility transistor (HEMT). Experimental results from a VMT realized using the AlGaAs/GaAs system are given. The VMT channel carrier population as a function of input gate voltage is calculated for HEMTs and VMTs using a one-dimensional (1-D) numerical model. This supports a proposed equivalent circuit model for the VMT, which is used to compare VMT performance to that of HEMTs. A noise model for the VMT is developed, and this model suggests that HEMT-like noise is achievable with good carrier confinement. The dual gate, dual-channel VMT, while more complex than the HEMT, may be useful in applications such as analog-to-digital converters (ADCs) and microwave amplifiers     

Multifrequency operation of a quenched-domain mode Gunn-effect device

The theoretical influence of harmonic signals, subharmonic signals, and nonharmonically related signals upon the characteristics of the quenched-domain mode of Gunn-effect devices is evaluated for an X-band device at 1.5 times threshold voltage.     

A simple model of a buried channel charge coupled device

A one-dimensional model of a buried channel CCD is presented. The potential equations, using the depletion region approximation are solved for a range of doping levels and stored charge. In this way values of device capacitance are calculated.It is shown that for a device with uniform layer and substrate dopings, the equations have an analytic solution. These solutions take a rather complicated form, but have a simple geometrical representation. A geometrical construction, based on field plots, is given. This construction may be used in the study of more general doping profiles.     

The effect of trench-gate-oxide structure on EPROM device operation

A floating-gate erasable programmable read-only memory (EPROM) cell with a thin trench-gate-oxide (TGO) structure near the drain region was fabricated using electron-beam lithography technology. Several promising advantages were found for the TGO cell. The writing time was measured to be 100 faster than conventional devices of the same dimensions. Two-dimensional (2-D) simulation of the TGO structure indicated that longitudinal and transverse channel electric fields are generated which simultaneously increase the hot-electron population in the channel and the injection efficiency into the floating gate. The devices exhibit high-transconductance, fast programming, good-tolerance to unintentional writing during readout, and potential for flash-erase application     

LSA operation of a gallium arsenide device in microstrip

Two LSA microstrip oscillators were made. The poor performance of the first oscillator was found by a time-domain computer simulation to be caused by poor circuit design and the effects of the LSA device package. A second circuit was constructed which eliminated the device package and used a more straightforward design. Thirty watts of RF power was generated in the second circuit at a frequency of 1.96 GHz, with an efficiency of 12.5 percent.     

The charge coupled device as an interdigitally distributed RC network

A charge coupled device with phasor sets in different structures is considered as an interdigitally distributed RC network, and is analyzed by small a.c. signal measurements. The bias voltage and a.c. frequency dependent admittances measured at source and/or drain diffusion terminals are used to characterize the electronic structure under each phasor set. An experimental example is illustrated by using a PCCD with four phasors in two oxide level sets. Oxide thicknesses, electron mobility and doping profiles of the ion-implant layer under each oxide level are obtained by applying the a.c. signal to each phasor set. Channel depth, epitaxial and substrate concentrations are also determined by applying the a.c. signal to the substrate terminal.     

The mechanism of charge transfer in Bi2(Te0.9Se0.1)3 solid solution thin films

The conductivity, Hall effect, and magnetoresistance of Bi₂(Te_0.9Se_0.1)₃ solid solution thin films are studied in a wide temperature range from 2.5 to 300 K and in high magnetic fields of up to 8 T. It is found that the conductivity of Bi₂(Te_0.9Se_0.1)₃ solid solution thin films is of the insulator type, whereas the conductivity of the corresponding bulk single crystals is of metallic type. It is inferred that, at high temperatures (100–300 K), the conductivity is controlled mainly by thermally activated charge-carrier transport over extended states in the conduction band, with an activation energy of about 15 meV. At lower temperatures (2.5–70 K), conductivity controlled by charge-carrier hopping between localized states in a narrow energy region close to the Fermi level is dominant. From the magnetoresistance and conductivity data, the localization radius, the density of localized states, and the average charge-carrier hopping length are estimated.     

Improved modulation performance of a silicon p-i-n device by trenchisolation

This paper reports on the simulation of the dc and transient performance of a p⁺-i-n⁺ single-mode optical phase modulator suitable for silicon-on-insulator material. An analysis of the variation in the dc and transient performance due to trench isolation has been carried out. The device has been modeled using the two-dimensional device simulation package SILVACO. SILVACO has been employed to investigate the overlap between the injected free carriers in the intrinsic region and the propagating optical mode. On forward bias of the device, free carriers are injected into the intrinsic guiding region of the device, resulting in a change in the refractive index of this region. The device studied is designed to support a single optical mode and is of multimicrometer dimensions, thus simplifying fabrication and allowing efficient coupling to/from single-mode fibers or other single-mode devices. The modeling indicates that increased dc device performance of up to 74% results from a vertical trench defined adjacent to the outer edge of the contact region, as compared to a device without trench isolation. For the same conditions an increase in the transient performance of ~18% is also observed     

具有互补电荷岛结构的PSOI高压器件

本文提出一种新的具有互补n+-电荷岛结构的PSOI高压器件（CNCI PSOI）。该结构在PSOI器件介质层上下界面分别注入形成一系列等距的高浓度n+区。器件外加高压时,在上下介质层的n+-区域之间形成互补的空穴和电子岛,因此能有效的增强界面电场(EI) 和提高耐压(BV),通过源下的硅窗口还能减小器件的自热效应。本文分析了CNCI PSOI 的垂直界面电场的模型,分析结果和二维仿真结果吻合。CNCI PSOI LDMOS 在较低的自热效应的情况下,BV 和EI从常规PSOI的 216V 和81.4V/μm 提高到591V 和512 V/μm。文中详细研究了结构参数对所提出的器件性能的影响。     

Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI(PSOI) high voltage device structure named CNCI PSOI(complementary n~+-charge islands PSOI) is proposed.CNCI PSOI is characterized by equidistant high concentration n~+ -regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device.When a high voltage is applied to the device,complementary holes and electron islands are formed on the two n~+-regions on the top and bottom interfaces,therefore effectively enhancing the electric field of the dielectric buried layer(E_I) and increasing the breakdown voltage (BV),alleviating the self-heating effect(SHE) by the silicon window under the source.An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results.BV and E_I,of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE,respectively.The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.     

The generation-recombination mechanism of charge transport in a thin-film CdS/CdTe heterojunction

An n-CdS/p-CdTe heterostructure is studied. The heterostructure is obtained using the sequential growth of CdS and CdTe layers by electrochemical deposition and closed-space sublimation, respectively. The measured current-voltage characteristics are interpreted in the context of the Sah-Noyce-Shokley generation-recombination model for the depletion layer of a diode structure. The theory quantitatively agrees with the experimental results.     

Gunn-effect memory device using the charge accumulation on a Schottky-trigger electrode

A new Gunn-effect memory device using the charge accumulation on a Schottky-trigger electrode is proposed and its operation demonstrated with a monolithically fabricated device. Theoretical calculations show that the device could be modified into a static memory device if the Schottky electrode potential is chosen as the output.