GaAs microwave power FET

A design consideration for an X-band GaAs power FET, features of the fabrication process, and electrical characteristics of the FET are described. Interdigitated 53 source and 52 drain electrodes and an overlaid gate electrode for connecting 104 Schottky gates in parallel have been introduced to achieve a 1.5-µm-long and 5200-µm-wide gate FET. A sheet grounding technique has been developed in order to minimize the common source lead inductance (L8= 50 pH). The resulting devices can produce 0.7-W and 1.6-W saturation output power at 10 GHz and 8 GHz, respectively. At 6 GHz, a linear gain of 7 dB, an output power of 0.85 W at 1-dB gain compression and 30-percent power added efficiency can be achieved. The intercept point for third-order intermodulation products is 37.5 dBm at 6.2 GHz.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

Demonstration of sub-5 ps CML ring oscillator gate delay withreduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT     

High-performance standard cell library and modeling technique fordifferential advanced bipolar current tree logic

A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 μm×2.4 μm and a maximum f _t of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees     

A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell

A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W.     

An 11-GHz GaAs frequency divider using source-coupled FET Logic

A GaAs one-fourth frequency divider is fabricated to evaluate the ultrahigh-speed performance of source-coupled FET logic (SCFL) having normally-on FET's with small negative V th values. High-transconductance (240 ms/mm) 1/2-µm gate-length FET's and an air-bridge interconnection line technology are successfully developed. A maximum toggle frequency Fmaxof 11 GHz is achieved with a power dissipation of 149 mW. Furthermore, 9.7-GHz Fmaxwith low power dissipation of 52 mW was also obtained.     

Ultra-high-speed digital circuit performance in 0.2-μmgate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2-μm gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g_m transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K     

Sub-400-ps ISL circuits

This paper describes advanced Integrated-Schottky-Logic (ISL) circuits featuring double-poly self-alignment, "free" epi-base lateral p-n-p clamp, self-aligned guard ring Schottky barrier diode, and silicon-filled trench isolation. Using a 0.7-µm-thick epitaxial layer and 1.2-µm minimum dimensions, gate delays of 432 ps (fan-out = 1) and 527 ps (fan-out = 3) are obtained at current levels of 183 and 255 µA/gate, respectively; with nonwalled emitter. With walled emitter (two sides), a gate delay of 382 ps is achieved for fan-out of 3 at a current level of 267 µA/gate.     

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured.<>     

An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications.     

Submicrometer insulated-gate inverted-structure HEMT for high-speed large-logic-swing DCFL gate

Application of insulated-gate inverted-structure HEMT (I²-HEMT) to the enhancement/depletion (E/D) type direct-coupled FET logic circuits has been investigated. Superior electric characteristics were attained in a submicrometer-gate FET and ring oscillator. The threshold voltage shift with a reduction of gate length from 1.2 to 0.7 µm was as small as -0.05 V at 300 K. Drain conductances were very small and were 2.0 and 3.6 mS/mm at 300 and 77K, respectively. Gate leakage current was small enough even at a gate voltage of + 1.4 V both at 300 and 77 K, and a logic swing of larger than 1.2 V was achieved using a DCFL inverter. A 21-stage E/D-type DCFL ring oscillator with an 0.8-µm gate length showed a minimum gate delay of as small as 18.0 ps at a low power dissipation of 520 µW/gate at 77 K. High-speed and large logic-swing characteristics of the I²-HEMT DCFL circuits are accomplished by forming an undoped AlGaAs layer as a gate insulator on the inverted-structure HEMT structure.     

Low-noise HEMT using MOCVD

Low-noise HEMT AlGaAs/GaAs heterostructure devices have been developed using metal organic chemical vapor deposition (MOCVD). The HEMT's with 0.5-µm-long and 200-µm-wide gates have shown a minimum noise figure of 0.83 dB with an associated gain of 12.5 dB at 12 GHz at room temperature. Measurements have confirmed calculations on the effect of the number of gate bonding pads On the noise figure for different gate Widths. Substantial noise figure improvement was observed Under low-temperature operation, especially compared to conventional GaAs MESFET's. A two-stage amplifier designed for DBS reception using the HEMT in the first stage has displayed a noise figure under 2.0 dB from 11.7 to 12.2 GHz.     

A microwave power double-heterojunction high electron mobility transistor

A microwave power high electron mobility transistor (HEMT) has been developed and tested in theK-band frequency range. The HEMT has a unique configuration of a selectively low-doped (AlGa)As/GaAs/(AlGa)As double heterojunction resulting in both capability of high-current density and high gate breakdown voltage. The structure showed electron mobility of 6800 cm²/V.s and two-dimensional (2-D) electron density as high as 1.2 × 10¹²cm^-2at room temperature. An output power of 660 mW (550 mW/mm) with 3.2-dB gain and 19.3-percent power added efficiency was achieved at 20 GHz with 1-µm gate length and 1.2-mm gate periphery. A similar device with 2.4-mm gate width produced an output power of 1 W with 3-dB gain and 15.5-percent efficiency. These results offer microwave high power capability in a double-heterojunction HEMT (DH-HEMT).     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

Deep submicrometer super self-aligned Si bipolar technology with25.4 ps ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-μm design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called “High-Performance Super Self-Aligned Process Technology” or HSST. 0.3-μm minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-μm SST-1B. Owing to its horizontal reduction and an f_T of 22.3 GHz at V_ce=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems     

Analysis of the properties of three-terminal transferred-electron logic devices

A two-dimensional analysis of Schottky-barrier gate GaAs logic devices utilizing the transferred-electron effect is described. The analysis is used to study the basic properties of two devices with anode to cathode spacing of 13 µm and 33 µm. The reduction in current drop due to the presence of the gate is discussed. The switching properties of the 13-µm device are studied for operation with either anode or cathode resistance. A gate delay of 30 ps and a total gate power of 180 mW is estimated.     

High-speed logic at 300K with self-aligned submicrometer-gate GaAs MESFET's

The fastest room-temperature logic gate operation yet reported has been achieved with an improved technology for self-aligned ion-implanted GaAs MESFET's. The procedure involves fabrication of 0.75/0.6-µm "T-gate" structures using electron-beam lithography, and employs arsenic-overpressure capless annealing of the self-aligned n⁺-implant. Minimum propagation delays of 15.4 ps/ stage were obtained for several of the ring oscillators, and none of the oscillators fabricated showed propagation delays longer than 17.0 ps. The fabrication technology and experimental results are described.