Optimization of nanoelectronic systems' reliability under massive defect density using cascaded R-fold modular redundancy

The theoretical analysis of R-fold modular redundancy, cascaded R-fold modular redundancy and NAND multiplexing is presented and these fault-tolerant techniques are compared in terms of resistance to massive levels of defect density. Optimal cluster size analysis and redundancy optimization of the cascaded R-fold modular redundancy technique has been performed for the first time in the context of a large-scale system. The optimal window of application of each fault-tolerant technique with respect to defect density is presented as a way to find the optimum design trade-off between the reliability and power/area. Building viable systems consisting of components with high defect densities in future nanoscale technologies will have a high cost in power/area, regardless of the fault-tolerant techniques used.     

Bifurcations and fundamental error bounds for fault-tolerant computations

In the emerging nanotechnologies, faulty components may be an integral part of a system. For the system to be reliable, the error of the building blocks has to be smaller than a threshold. Therefore, finding exact error thresholds for noisy gates is one of the most challenging problems in fault-tolerant computations. Under the von Neumann's probabilistic computing framework, we show that computation by circuits built out of noisy NAND gates with an arbitrary number of K inputs under worst case operation can be readily described by nonlinear discrete maps. Bifurcation analysis of such maps naturally gives the exact error thresholds above which no reliable computation is possible. It is further shown that the maximum threshold value for a K-input NAND gate is obtained when K=5. This implies that if one chooses NAND gate as basic building blocks, then the optimal number of inputs for the NAND gate may be very different from the conventional value of 2. The analysis technique generalizes to other types of gates and circuits that use voting to improve reliability, as well as a network built out of the so-called para-restituted NAND gates recently proposed by Sadek et al. Nonlinear dynamics theory offers an interesting perspective to study rich nonlinear interactions among faulty components and design nanoscale fault-tolerant architectures.     

Analytical Models for the Performance of von Neumann Multiplexing

As conventional silicon CMOS technology continues to shrink, logic circuits are increasingly subject to errors induced by electrical noise. In addition, device reliability will become a problem, and circuits will be subject to permanent faults. Rather than requiring the circuit to be defect-free, fault-tolerance techniques can be incorporated to allow the continued operation of these devices in the presence of defects. We present an improved model for the reliability of nand multiplexing, a fault-tolerance technique typically requiring large levels of redundancy. It extends previous models to account for dependence between the inputs and derives the distribution of the outputs of each stage when subject to errors. The Markov chain approach used in earlier models is shown to be correct in modeling the effect of multiple stages. Our new model produces more accurate results for moderate levels of redundancy. An example shows the required hardware redundancy is reduced by 50% versus the previous binomial model. In addition, three new types of errors are modeled: the output stuck-at-one, output stuck-at-zero, and input stuck-at-zero faults     

Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic

To make digital circuits with unreliable devices more reliable has been a design challenge, especially for today's nanometer-scale technologies. In this paper, we discuss gate replication architecture towards increasing the reliability of individual logic gates. While this architecture is similar to, and a special case of, conventional N-modular redundancy scheme, we provide more interpretation and extend it to the situation where N is an even integer by using threshold logic gate instead of majority voter. We also study the reliability models for generic gates with single-electron tunneling (SET) technology. Both analysis and numerical evaluation suggest that while more redundancy leads to higher reliability in general, the improvement rate depends on individual gate failure rates     

Markov chains and probabilistic computation-a general framework for multiplexed nanoelectronic systems

In emerging nanotechnologies, reliable computation will have to be carried out with unreliable components being integral parts of computing systems. One promising scheme for designing these systems is von Neumann's multiplexing technique. Using bifurcation theory and its associated geometrical representation, we have studied a NAND-multiplexing system recently proposed. The behavior of the system is characterized by the stationary distribution of a Markov chain, which is uni- or bi-modal, when the error probability of NAND gates is larger or smaller than the threshold value, respectively. The two modes and the median of the stationary distribution are the keys to the characterization of the system reliability. Examples of potential future nanochips are used to illustrate how the NAND-multiplexing technique can lead to high system reliability in spite of large gate error probability while keeping the cost of redundancy moderate. In nanoelectronic systems, while permanent defects can be taken care of by reconfiguration, probabilistic computation schemes can incorporate another level of redundancy so that high tolerance of transient errors may be achieved. The Markov chain model is shown to be a powerful tool for the analysis of multiplexed nanoelectronic systems.     

Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures

Motivated by the need for economical fault-tolerant designs for nanoarchitectures, we explore a novel multiplexing-based redundant design scheme at small (/spl les/100) and very small (/spl les/10) redundancy factors. In particular, we adapt a strategy known as von Neumann multiplexing to circuits of majority gates with three inputs and for the first time exactly analyze the performance of a multiplexing scheme for very small redundancies, using combinatorial arguments. We also develop an extension of von Neumann multiplexing that further improves performance by excluding unnecessary restorative stages in the computation. Our results show that the optimized three-input majority multiplexing (MAJ-3 MUX) outperforms the latest scheme presented in the literature, known as parallel restitution (PAR-REST), by a factor between two and four, for 48/spl les/R/spl les/100. Our scheme performs extremely well at very small redundancies, for which our analysis is the only accurate one. Finally, we determine an upper bound on the maximum tolerable failure probability when any redundancy factor may be used. This bound clearly indicates the advantage of using three-input majority gates in terms of reliable operation.     

电涡流传感器阵列测试技术

针对采用扁平柔性电涡流传感器阵列实现大面积金属曲面部件位置实时监测,对电涡流传感器的阵列测试技术进行了研究.采用一种基于时分多路的电涡流阵列测试的方法,通过对传感器探头和测试电路的合理设计,使系统电路得到简化,减小阵列单元之间的串扰,提高传感器系统的测试性能,实现了电涡流传感器阵列的快速、高精度测量.     

Implementation of high speed optical universal logic gates using the electro-optic effect-based Mach–Zehnder interferometer structures

The universal logic gates are the most important logic gates responsible for optimized design of different types of complex digital logic circuits. It is of great interest to implement the function of universal logic gates such as NAND and NOR logic gates using the concepts of electro-optic effect. The smart use of electro-optic effect can provide very effective optical power switching devices. The implementation of universal logic gates operation in the optical domain can improve the performance of the devices and includes the advantages of the optical communication system. The proper configuration of Mach–Zehnder interferometer working on the principle of electro-optic effect can provide the optical responses equivalent to the NAND and NOR logic gates. The proposed devices can be analyzed to check the various performance affecting parameters in order to specify the physical parameters.     

基于 NAND Flash 的嵌入式文件系统设计

主要介绍了针对 NAND Flash 型存储器设计的嵌入式文件系统. 其硬件平台是为了顺应多功能、大容量集成化存储的需求而开发的基于 ADSP-BF532 芯片与 NAND Flash 结合的高性能嵌入式存储系统. 此存储系统采用了多片并行流水的存储模式,开发出独特有效的闪存管理技术与改良的文件系统,通过设置访问权限实现多用户管理,使得处理器、存储器以及文件管理层软件的多方优势得以充分发挥.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

Reliability measurement of mass storage system for onboard instrumentation

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are the commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments, such as extreme radiation, can be experienced throughout the mission. Acceptable dependability for these instruments has been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering . This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a reliable foundation of measurement. Then, lifelong dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of the reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (i.e., the expected time that a system will operate before it fails). Finally, minimal column redundancy search technique for the fault-tolerant memory system is proposed and verified through a series of parametric simulations. Thereby, design and fabrication of cost-effective and highly reliable fault-tolerant onboard mass storage system can be realized for dependable instrumentation.     

Nanocomputing by field-coupled nanomagnets

Demonstrates through simulations the feasibility of using magnetically coupled nanometer-scale ferromagnetic dots for digital information processing. Microelectronic circuits provide the input and output of the magnetic nanostructure, but the signal is processed via magnetic dot-dot interactions. Logic functions can be defined by the proper placements of dots. We introduce a SPICE macromodel of interacting nanomagnets and use this tool to design and simulate the proposed nanomagnet logic units. This SPICE model allows us to simulate such magnetic information processing devices within the same framework as conventional electronic circuits.     

基于嵌入式系统的NANDFlash坏块处理和FMM实现

随着嵌入武产品的不断发展,对存储设备的要求也越来越高.本文以NANDFlash为例,介绍了大容量NANDFlash在嵌入式系统中的设计与应用,并提出了一种消除文件写入NANDFlash时出现坏块影响的方法.同时对基于NANDFlash的管理软件FMM的实现算法进行了优化,提高了效率和性能.     

Plasmon resonance in individual nanogap electrodes studied using graphene nanoconstrictions as photodetectors

We achieve direct electrical readout of the wavelength and polarization dependence of the plasmon resonance in individual gold nanogap antennas by positioning a graphene nanoconstriction within the gap as a localized photodetector. The polarization sensitivities can be as large as 99%, while the plasmon-induced photocurrent enhancement is 2-100. The plasmon peak frequency, polarization sensitivity, and photocurrent enhancement all vary between devices, indicating the degree to which the plasmon resonance is sensitive to nanometer-scale irregularities.     

A new universal gate for low power SoC applications

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.     

Cold-standby redundancy optimization for nonrepairable systems

A solution methodology is described and demonstrated to determine optimal design configurations for nonrepairable series-parallel systems with cold-standby redundancy. This problem formulation considers non-constant component hazard functions and imperfect switching. The objective of the redundancy allocation problem is to select from available components and to determine an optimal design configuration to maximize system reliability. For cold-standby redundancy, other formulations have generally required exponential component time-to-failure and perfect switching assumptions. For this paper, there are multiple component choices available for each subsystem and component time-to-failure is distributed according to an Erlang distribution. Optimal solutions are determined based on an equivalent problem formulation and integer programming. Compared to other available algorithms, the methodology presented here more accurately models many engineering design problems with cold-standby redundancy. Previously, it has been difficult to determine optimal solutions for this class of problems or even lo efficiently calculate system reliability. The methodology is successfully demonstrated on a large problem with 14 subsystems.     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon memory device with different tunneling oxide thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.     

Tribotronic triggers and sequential logic circuits

In this paper,a floating-gate tribotronic transistor (FGTT) based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor (FET) is proposed.In the FGTT,the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor.Based on the FGTTs and FETs,a tribotronic negated AND (NAND) gate that achieves mechanical-electrical coupled inputs,logic operations,and electrical level outputs is fabricated.By further integrating tribotronic NAND gates with traditional digital circuits,several basic units such as the tribotronic S-R trigger,D trigger,and T trigger have been demonstrated.Additionally,tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation.In contrast to the conventional sequential logic units controlled by electrical signals,contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment.This development can lead to their potential application in micro/nano-sensors,electTomechanical storage,interactive control,and intelligent instrumentation.     

Capacitively-Coupled SQUID Bias for Time Division Multiplexing

The multiplexing scheme presented in this paper is part of the readout chain of the QUBIC instrument devoted to cosmic microwave background polarization observations. It is based on time domain multiplexing using superconducting quantum interference devices (SQUIDs) to read out a large array of superconducting bolometers. The originality of the multiplexer presented here lies in the use of capacitors for the SQUID addressing. Capacitive coupling allows us to bias many SQUIDs in parallel (in a 2D topology), with low crosstalk and low power dissipation of the cryogenic front-end readout. However, capacitors in series with the SQUID require a modification of the addressing strategy. This paper presents a bias reversal technique adopted to sequentially address the SQUIDs through capacitors using a cryogenic SiGe integrated circuit. We further present the different limitations of this technique and how to choose the proper capacitance for a given multiplexing frequency and current source compliance.