Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.     

Output characteristics model for an a‐Si ISFET pH sensor

A mathematical model for the calculation of the output characteristics of amorphous silicon hydrogenated (a‐Si:H) ion‐sensitive field‐effect transistors (ISFET) is developed, which depends on the integration of the conductivity channel versus gate voltage curve at fixed drain voltage. Single curve integration was changed to integration with many simple lines to obtain the I_D − V_D characteristics using computer programming. The results of this model were tested with those of experiments. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Fabrication and Characterization of Gate-Connected 1T2C-Type Ferroelectric Memory with Paired Bi4 − xLaxTi3O12 Capacitors

A gate-connected 1T2C-type ferroelectric memory, in which the bottom electrodes of paired ferroelectric capacitors are connected to the gate electrode of an underlying FET (field effect transistor) on the field oxide region, was fabricated using a Bi_{4 ? x}La_xTi₃O₁₂ (BLT) film and its electrical properties were characterized. The I_D-V_G (drain current-gate voltage) characteristics of a FET combined with a single ferroelectric capacitor showed that the paired capacitors had almost the same ferroelectric property. It was found in the readout operation that there existed an optimum voltage to maximize the drain current on/off ratio between datum ‘1’ and datum ‘0,’ and that the maximum ratio was as large as 6 × 10⁴. It was also found that the drain current level remained constant, even if the readout operation was repeatedly conducted. It was concluded from these results that the 1T2C-type memory was successfully fabricated using the proposed process and operated properly.     

Simulation of Lag Phenomena and Pulsed I-V Curves of Compound Semiconductor FETs as Affected by Impact Ionization

Turn-on characteristics of GaAs MESFETs are simulated when the gate and the drain voltages are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is discussed how the slow current transients (lag phenomena) and the pulsed I-V curves are affected by the existence of substrate traps and surface states. It is also discussed how the characteristics are influenced by impact ionization of carriers.     

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (R_SiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V_t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C_G) are estimated with respect to different gate length (L_G), gate bias (V_G), and R_SiGe. For short channel effects, such as V_t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D-V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.     

A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I_D−V_G, I_D−V_D, transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.     

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab . The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, I_d‐V_gs, I_d‐V_ds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Deterioration of device characteristics of MFSFET due to fatigue

Abstract

Change of device characteristics of the metal-ferroelectric-semiconductor FET (MFSFET) with the progress of fatigue of the ferroelectric thin film are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V_G curves exhibit the accumulation, the depletion and inversion regions clearly. They also exhibit the memory window of 2V. I_D-V_D curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I_D-V_D curve is 6mA/cm², which decreases as much as 50% after fatigue. Our model is expected to be very useful in the estimation of the behaviour of MFSFET devices with the progress of fatigue.     

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the I_ON/I_OFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, S_Vth (the V_th sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a S_Vth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

     

Full Band Monte Carlo Simulation of Wurtzite AlGaN/GaN MODFETs

We present full band Monte Carlo simulations of a wurtzite Al_0.15Ga_0.85N/GaN modulation-doped field-effect transistor (MODFET). We found that without inclusion of the piezoelectric effect, the electron concentrations in the channel are much lower than obtained from experimental data. The calculated I _ds-V _ds curves show a strong negative differential resistance, which is a feature observed in experimental devices. Self-heating effects are usually believed to be the main cause of the negative differential resistance. Our simulations do not include self-heating, and this would indicate that at least part of what is observed is also caused by the drift-velocity behavior vs. electric field of the narrow conduction channel. For a 0.2 m gate MODFET, the simulations yield a maximum trans-conductance G _m 250 mS/mm with V _G = 1.0 V and V _ds = 5.0 V. When V _G = 0.0 V and V _ds = 8.0 V, we obtain a maximum cutoff frequency f _T = 180 GHz with I _d = 1159 mA/mm.     

Ferroelectric memory FET with Ir/IrO2 electrodes

Abstract

We proposed a MFMIS structure having a floating gate as a bottom electrode between a ferroelectric thin film and the gate SiO₂. Conventional gate SiO₂ can be used and ferroelectric thin films can be grown on bottom electrodes which have a good matching with the ferroelectric materials due to adopt the MFMIS structure. Ir and IrO₂ on poly-Si were used as floating gate. When a IrO₂ layer was formed between PZT and poly-Si, a high-quality PZT thin film was obtained and the PZT films show no fatigue up to 10¹² cycles of switching pulses. From the I_D-V_G characteristics measurement for 1·2 μm P-ch MFMIS FET, the shift in V_th or the memory window for a bias sweep of ±15V was about 3·3V. The difference of I_D-V_D curves which corresponded to I_D-V_G characteristics were found between before and after a programming pulse was applied.     

Interface Characterization of All-Perovskite Oxide Field Effect Heterostructures

All-oxide devices consisting of Niobium-doped Strontium Titanate (Nb:STO)/Strontium Titanate (STO)/Lanthanum Strontium Cuprous Oxide (LSCO) heterostructures were fabricated and characterized electrically for their interface properties through capacitance-voltage (C-V) and current-voltage (I-V) techniques, in the context of electric field effect studies. The C-V studies establish the occurrence of charge modulation in the LSCO channel. Absence of hysteresis in the C-V characteristic when the voltage is retraced suggests the absence of mobile ions in the gate oxide and slow interface traps. This is further corroborated by the absence of drift in the C-V characteristic and shift in the flat band voltage (V _FB) when the device is subjected to temperature-bias aging. The interface state density obtained from V _FB is 10¹²/cm². The uncompensated hole concentration in the LSCO channel calculated from the measured room temperature C-V data is 10²⁰/cm³ and is in good agreement with the expected hole concentration in LSCO. Current-time and current-voltage plots are invariant with respect to the polarity of the applied voltage up to 5 V. This, in a structure with asymmetric interfaces, indicates that the electrical contacts to STO are non-blocking and the conduction through STO is bulk-limited in this voltage regime. Thickness dependent current and capacitance studies also corroborate the bulk-limited nature of conduction through the device in this voltage regime. However, I-V characteristic shows a rectifying nature beyond 8 V indicating that the mechanism in this voltage regime could be interface limited.     

Diagnosis of Stator‐Winding‐Turn Faults of Induction Motor by Direct Detection of Negative Sequence Currents

In an AC motor, the quick detection of an initially small fault is important for preventing any consequent large fault. Various detection approaches have been proposed in previous papers, for example, by the Park vector (PV), AI techniques, wavelet analysis, and negative sequence analysis. This paper proposes a method for diagnosing a stator winding fault in an induction motor by the direct detection of its negative sequence current. Before starting the diagnosis, the asymmetry admittances for the considered fault cases are obtained by analysis or simulation. The amplitude and phase of the positive sequence voltage, V_p, and of the positive sequence current, I_p, are extracted from the voltage PV and current PV, respectively. The amplitude and phase of the negative sequence, I_n, are extracted from the residue. The asymmetry admittance, Y_a, is calculated from I_n and V_p. When the positive sequence admittance is known, Y_a can also be calculated from Y_p, I_p, and I_n. These steps are repeated for each sample time and the motor condition is diagnosed according to the variations in the Y_a values. The simulation and experimental results are also shown, and the proposed method is investigated and validated. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(3): 75–84, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22350     

Classification of ground faults in distribution lines according to phase-plane trajectories of waveforms

Recently, a greater demand for stable supply of electric power has resulted from a higher standard of living. It becomes important that the causes and locations of ground faults in distribution lines be found early and defects be repaired as soon as possible. Therefore, a unit for recording the waveform I₀ of ground fault's current and the waveform V₀ of its voltage is installed in distribution substations. The establishment of a technology to distinguish fault causes automatically is being hastened. This paper presents a new classification method for ground fault waveforms, based on phase-plane trajectories for the current or voltage and their differential values. Examinations of ground fault waveforms based on real data show that the waveform of current I₀ is more suitable than that of voltage V₀ for the classification of waveforms at ground faults and that the trajectory of each of the three types of waveforms, such as sine waves, trapezoidal waves, and spikes, has all of the characteristics in its figure. It is also found from the distribution of 167 sampling points on the phase plane that any waveforms at a real ground fault may be classified into three characteristic point distributions, which gives the possibility of easy display for the classification of ground fault causes. © 1998 Scripta Technica. Electr Eng Jpn, 122(1): 8–16, 1998     

Design, fabrication and characterization of dual-channel real space transfer transistor

In this paper, using a δ-doping dual-channel structure and GaAs substrate, a real space transfer transistor (RSTT) is designed and fabricated successfully. It has the standard Λ-shaped negative resistance I–V characteristics as well as a level and smooth valley region that the conventional RSTT has. The negative resistance parameters can be varied by changing gate voltage (V _GS). For example, the PVCR varies from 2.1 to 10.6 while V _GS changes from 0.6 V to 1.0 V. The transconductance for I _P (ΔI _P/ΔV _GS) is 0.3 mS. The parameters of V _P, V _V and threshold gate voltage (V _T) for negative resistance characteristics arising are all smaller than the value reported in the literature. Therefore, this device is suitable for low dissipation power application. __________ Translated from Journal of Semiconductors, 2008, 29(1): 136–139 [译自: 半导体学报]     

Loss analysis based on constant gate current for MOSFET selection of CCM boost converter

Predicting the power losses in a semiconductor is an essential design process to determine the converter's size. In the continuous conduction mode (CCM) boost converter, the power loss of MOSFETs can be divided into the loss not depending on the gate current (the conduction loss) and losses depending on the gate current (the switching losses) leading to I_DS transition period and V_DS transition period. Therefore, analysis of both conduction and switching losses based on constant gate current can realize the MOSFET selection to improve the efficiency of the CCM boost converter.     

New current–voltage transferring device with different metals

A new concept of an electrical shunt with different materials (aluminum and copper) has been developed to be used as an alternative current measurement device. The device provides better current measurement characteristics compared with the conventional current measurement devices such as a shunt resistor with an ammeter or the multiple shunts consisting of molybdenum having a low temperature coefficient and a Rogowski coil with an integrated circuit. The currents in several electrical circuits have been measured using the developed current–voltage transferring device (CVTD) as voltages between the aluminum and copper elements. The measured voltages (V_m) are proportional to measuring currents (I_m), which is shown as the following the experimental equation V_m [mV] =kI_m [A], in which k is a coefficient depending on the configuration of the CVTD. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.