Planar multilevel interconnection technology employing a polyimide

A planar multilevel interconnection technology, called planar metallization with polymer (PMP), has been developed, which utilizes a polyimide known as PIQ (polyimide isoindroquinazoline-dione) as an interlevel dielectric. The PIQ is highly resistant to heat and is mechanically flexible. Its low impurity concentrations also make it very stable in semiconductors. The PMP processing techniques have been refined to the stage where ICs can be fabricated commercially. A PIQ film etchant forms fine via-holes up to 3/spl times/3 /spl mu/m/SUP 2/, and chip size can be reduced by placing bonding pads on the active region of the device. Highly reliable linear and 256-bit bipolar memory ICs have been realized through this technology.     

Flip-chip on flex integrated power electronics modules for high-density power integration

Three-dimensional flip-chip on flex (FCOF) integrated power electronics modules (IPEMs) have been fabricated for high-density power applications. In this FCOF-IPEM structure, solder-bumped devices were flip-soldered to a flexible substrate with electrical circuits etched on both sides. One side of the flex provides interconnection to power devices while the other is used to construct a simple gate-drive circuit; via holes through the flex integrate the power stage and gate-drive together. Solder-bumped MOSFET devices were obtained by a metallization processing and were used in the FCOF power module construction to improve thermal performance, power density, and integration. With this packaging approach, the multiple solder bumps, instead of the thin, long bonding wires were utilized to connect the power devices to the flex substrate and to improve heat dissipation, lower parasitic oscillations, and reduce package size. Reliability of solder joints has been dealt with through selection of materials, such as use of flexible substrates and underfill encapsulation, and design of joint shape for lower thermomechanical stresses. A comparative study of continuous switching test results have shown that the FCOF-IPEMs have better electrical performance than commercial wire bonded power modules.     

Embedded power: a 3-D MCM integration technology for IPEM packaging application

Embedded power (EP) is the name for an integration technology for the power electronics switching stage, in which the multiple bare power chips, such as IGBTs, MOSFETs, and diodes, are buried in a ceramic frame and covered by a dielectric layer with via holes on the Al pads of the chips. Then, a planar metallization pattern is deposited onto it both for bonding to the power chips and a circuit wiring. The ceramic frame can be used as an extra thermal path and substrate for fabrication of the hybrid circuit with compatible thin- or thick-film techniques. When this integrated chips component is stacked with a base substrate and the associated components, a novel three-dimensional (3-D) multichip module (MCM) is produced. Such an integrated power electronics module (IPEM) offers performance improvement, functional integration, and process integration, as compared to conventional power hybrid modules. This paper presents the details of this technology, including the process design and implementation. A subsystem IPEM, incorporating power factor correction (PFC) and dc/dc switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized to demonstrate the feasibility of this power electronics integration technology. The capability for functional integration and the electrical performance improvement, which includes reduction in parasitics and increase in efficiency, are presented.     

Signal integrity analysis of system interconnection module of high‐density server supporting serial RapidIO

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high‐density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack‐up types on a printed circuit board. Each module was designed into 12‐ (version 1) and 14‐layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high‐speed signal‐layers in the middle of two power planes, whereas Version 2 has a single high‐speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S‐parameters, eye‐diagrams, and crosstalk voltages. The results show that the high‐speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.     

High Temperature Embedded SiC Chip Module (ECM) for Power Electronics Applications

Technology for a 3-D high temperature integrated power electronics module for applications involving high density, and high temperature (e.g., those over 200degC) is described. The high temperature embedded chip module (ECM) technology is proposed to realize a lower stress distribution in a mechanically balanced structure with double-sided metallization layers and material coefficient of thermal expansion match in the structure. This technology for packaging the active component is also proposed for universal use with a flip-over structure and pressure connections. The fabrication process of this high temperature ECM is presented. The forward and reverse characteristics of the high temperature ECM have been measured up to 279degC. Thermally induced mechanical stress is reduced to an acceptable level by applying a symmetrical structure with buffering layers     

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.     

Estimation of the degradation rate of multi-crystalline silicon photovoltaic module under thermal cycling stress

The overall power of an outdoor-exposed photovoltaic (PV) module decreases as a result of thermal cycling (TC) stress, due to the formation of cracks between the solder and metal. In this study, the thermal fatigue life of solder (62Sn36Pb2Ag) interconnection between copper and silver metallization in PV module was studied. This paper describes in detail the degradation rate (R_D) prediction model of solder interconnection for crystalline PV module. The R_D prediction model is developed which based on published constitutive equations for solder and TC test results on actual PV module. The finite element method was employed to study the creep strain energy density of solder interconnections in TC conditions. Three types of accelerated tests were conducted to determine the prediction model parameters. R_D in benchmark condition is predicted and compared with those of TC conditions.     

SnAg Microbumps for MEMS-Based 3-D Stacks

Fine pitch 100-$mu{rm m}$ electroplated SnAg microbump interconnection technology is presented and discussed for use in microelectromechanical systems (MEMS) based 3-D stacks. Electrochemical deposition (ECD) of copper top side metallization (TSM) is compared to performance of nickel–copper TSM on substrate chips. Nickel–copper was selected for under bump metallization (UBM) of die chips. Lead free Sn3.5%Ag was deposited on the die chip UBM and chip-to-wafer bonded by a standard SnAg reflow process in inert atmosphere. An automotive application module was selected as target application for investigating reliability and failure mechanism of the interconnection technology. Bonded units have been investigated by mechanical and physical analysis, visual inspection and electrical resistance measurements after assembly and subsequent environmental stress test including thermal cycling, elevated temperature, humidity, and high current. The fine pitch lead free microbumps displayed promising capability for 3-D stacking of silicon devices. Excellent performance under thermal cycling with no global thermal mismatch was demonstrated. The microbump interconnection technology proved to be tolerant to high temperature and extensive current exposure. TSM consumption and intermetallic compound (IMC) formation were less evident for the nickel–copper TSMs compared to those entirely made of copper. Only minor Kirkendall porosity was observed at the solder alloy interfaces in the present study.      

碳化硅功率器件高密度互连技术研究进展

相比于硅,SiC材料因具有宽禁带、高导热率、高击穿电压、高电子饱和漂移速率等优点而在耐高温、耐高压、耐大电流的高频大功率器件中得到了广泛应用。传统的引线键合是功率器件最常用的互连形式之一。然而,引线键合固有的寄生电感和散热问题严重限制了SiC功率器件的性能。文章首先介绍了硅功率器件的低寄生电感和高效冷却互连技术,然后对SiC功率器件互连技术的研究进行了综述。最后,总结了SiC功率器件互连技术面临的挑战。     

基于RocketIO接口的高速互连应用研究与实现

在此立足于嵌入式应用的背景,在理解RapidIO协议和Fibre Channel协议的基础上,通过对嵌入在FPGA内的RoeketIO高速串行收发器工作原理的研究,结合某信号处理接口模块的实际应用,在系统内实现RapidIO接口功能,在系统间实现FibreChannle接口功能,总结出基于RocketIO接口的高速信号完整性设计的应用特点,并进行简单的链路传输特性的测试,为高速互连系统的设计与研究提供了可靠的技术支撑。     

Polyimide liftoff technology for high-density LSI metallization

A new liftoff technology, in which a metallization layer can be deposited at high temperatures, is developed to provide two-level highly packed interconnection metallization. A heat-resistant polymide, PIQ^®, is employed as the liftoff layer. The reverse pattern of the metallization is formed by reactive sputter etching of the PIQ layer around a thin Mo mask. After metallization layer deposition, lift-off is carried out by electrolytic etching of the Mo mask, thus removing the layer deposited on PIQ. A higher packing density of interlevel connection is also accomplished by adopting exposed via holes. Utilizing this technology, fine-featured smoothly tapered metallization patterns can be obtained almost irrespective of the underlying topology. The minimum pitches of the first level, second level, and via holes are 5, 7, and 7 µm, respectively. This technology does not appear to be detrimental to bipolar device characteristics. A 4096-bit high-speed bipolar memory LSI with two-level highly packed interconnection metallization was produced experimentally utilizing this liftoff technology.     

芯片制造的电化学处理技术

电化学处理技术的性价比优势在芯片制造上是一个范例转移。Cu芯片金属化的双大马士革处理和面阵列芯片封装互连的C4(倒装)技术使电化学技术置于最复杂的制造工艺技术之间。这些工艺技术被集成到用于芯片制造的300mm晶圆处理中。新材料和工艺的持续发展来满足微处理器件不断增加性能和小型化的趋势。电迁移问题和集成超低k电介质材料与Cu镀层的新抛光方法是芯片制造中的一个关键问题。发展一个适用成本低的无铅C4芯片封装互连是微电子工业的主要目标,微电子工业正作努力在几年里市场化无铅产品。     

基于RapidIO协议的高速数据互联模块设计

RapidIO技术是目前世界上第一个、也是惟一的嵌入式系统互连国际标准,可以简单、高效、可靠地实现从单板到全系统的互连,在高性能数字信号处理系统中得到广泛的应用。介绍了基于RapidIO协议的高速数据互联模块的设计方案、高速数据传输设计中的难点、以及模块的信号完整性分析。该模块现已在雷达信号处理系统中得到应用验证,各项性能指标均能够满足应用需求,实现了可靠稳定的高速数据传输。     

系统级封装新型埋入式电源滤波结构的研究

在高密度小尺寸的系统级封装(SiP)中,对供电系统的完整性要求越来越高,多芯片共用一个电源网路所产生的电压抖动除了会影响到芯片的正常工作,还会通过供电网路干扰到临近电路和其他敏感电路,导致芯片误动作,以及信号完整性和其他电磁干扰问题.这种电压抖动所占频带相当宽,几百MHz到几个GHz的中频电源噪声普通方法很难去除.结合埋入式电容和电源分割方法的特点,提出一种新型高性能埋入式电源低通滤波结构直接替代电源/地平面.研究表明,在0.65～4GHz的频带内隔离深度可达-40～75 dB,电源阻抗均在0.25ohm以下,实现了宽频高隔离度的高性能滤波作用.分别用电磁场和广义传输线两种仿真器模拟,高频等效电路模型分析这种低通滤波器的工作原理以及结构对隔离性能的影响,并进行了实验验证.     

Investigation of the heel crack mechanism in Al connections for power electronics modules

In power electronic packages, one of the main limiting factors for the module reliability stems from failure of the electrical interconnection which ensures the contact between the chip and the lead frame. The aim of this work is to model, using FEM and some analytical developments, the interconnection heel crack mechanism appearing in service. The forming process impact is particularly evaluated and it is established that the initial residual stresses contribute to limit the wire/ribbon life time.     

用于系统级封装的毫米波介质填充波导的研究

基于不断发展的系统级封装技术,提出了一种用于芯片间高速互连的新型可集成的物理器件:硅基毫米波介质填充波导。文中阐述了该器件的物理原理,采用建模、仿真相结合的方法对该模块进行了结构设计,利用新的设计思路结合半导体工艺解决了毫米波互连结构内部的反射、电压驻波比(VSWR)、信号耦合、准TEM-TE-准TEM转换传输问题以及毫米波互连结构阵列中信号泄露的问题,并利用半导体与MEMS加工工艺加以实现。测试结果表明宽度为680μm的单通道矩形波导,-10 d B带宽为9.8 GHz,相对带宽为12.56%;传输损耗为1 d B/cm,工作频带内相邻波导之间串扰低于-40 d B,可以形成大阵列并进行集成,从而实现芯片间数据的并行传输。     

化学机械抛光中的颗粒技术

多层金属化是集成芯片以摩尔定律的速度更替的重要工艺手段.在多层金属化中,平坦的晶圆表面对每道工序的成功完成都是非常必要的,而化学机械抛光工艺能在每道工序之前将晶圆表面抛光.化学机械抛光主要是通过使用颗粒研浆去除材料来实现晶圆抛光.除了研浆本身的化学性质外,研浆的效果也受研磨颗粒性质的影响.如果我们能够更好的理解研磨颗粒...     

Electromagnetic design optimization tool for resonant integrated spiral Planar Power passives (ISP/sup 3/)

The electromagnetic integration of multiple passive components into a single integrated planar power passive module has been shown to be viable, not only for resonant structures, but recently also for nonresonant applications. Recent improvements in electromagnetic design and loss modeling for a resonant integrated spiral planar power passive (ISP/sup 3/) structures have made it possible to accurately estimate the electromagnetic characteristics of the structure before construction. In this paper, this improved modeling forms the basis of an approach for electromagnetically optimizing the structure. A graphical interface tool for identifying trends in resultant structure parameters with respect to design variables is presented. The graphical interface is also used to evaluate different possible optimization criteria. Using a simple optimization criterion, two improved prototype designs are developed and constructed. Finally, these two prototypes are then experimentally tested and compared with a prior state of the art design. These two resultant improved prototypes yield more than a doubling in structure power density without a decrease in structure efficiency. The relatively low resultant temperature differential within the prototypes shows that a substantial increase in power density is still possible and this can be effectively exploited if accurate thermal modeling is included in the future design optimization process.     

Cover Picture: Fabrication of Stable Metallic Patterns Embedded in Poly(dimethylsiloxane) and Model Applications in Non‐Planar Electronic and Lab‐on‐a‐Chip Device Patterning (Adv. Funct. Mater. 4/2005)

A composite image is shown that highlights examples of device architectures that either incorporate or exploit polymer‐embedded metallic microstructures. In work reported by Nuzzo and co‐workers on p. 557, new applications of soft lithography, in conjunction with advanced forms of multilayer metallization, are used to construct these exceptionally durable structures. They are suitable for use in non‐planar lithographic patterning, and as device components finding applications ranging from microelectronics to Lab‐on‐a‐Chip analytical systems. This article describes the fabrication of durable metallic patterns that are embedded in poly(dimethylsiloxane) (PDMS) and demonstrates their use in several representative applications. The method involves the transfer and subsequent embedding of micrometer‐scale gold (and other thin‐film material) patterns into PDMS via adhesion chemistries mediated by silane coupling agents. We demonstrate the process as a suitable method for patterning stable functional metallization structures on PDMS, ones with limiting feature sizes less than 5 μm, and their subsequent utilization as structures suitable for use in applications ranging from soft‐lithographic patterning, non‐planar electronics, and microfluidic (lab‐on‐a‐chip, LOC) analytical systems. We demonstrate specifically that metal patterns embedded in both planar and spherically curved PDMS substrates can be used as compliant contact photomasks for conventional photolithographic processes. The non‐planar photomask fabricated with this technique has the same surface shape as the substrate, and thus facilitates the registration of structures in multilevel devices. This quality was specifically tested in a model demonstration in which an array of one hundred metal oxide semiconductor field‐effect transistor (MOSFET) devices was fabricated on a spherically curved Si single‐crystalline lens. The most significant opportunities for the processes reported here, however, appear to reside in applications in analytical chemistry that exploit devices fabricated using the methods of soft lithography. Toward this end, we demonstrate durably bonded metal patterns on PDMS that are appropriate for use in microfluidic, microanalytical, and microelectromechanical systems. We describe a multilayer metal‐electrode fabrication scheme (multilaminate metal–insulator–metal (MIM) structures that substantially enhance performance and stability) and use it to enable the construction of PDMS LOC devices using electrochemical detection. A polymer‐based microelectrochemical analytical system, one incorporating an electrode array for cyclic voltammetry and a microfluidic system for the electrophoretic separation of dopamine and catechol with amperometric detection, is demonstrated.     

LTCC 450 MHz CDMA功放模块的研制

对LTCC埋层电感进行了研究,以研制体积小、低损耗、微波性能好的高密度功放模块。利用商用三维电磁场分析软件HFSS对LTCC集成化功率放大器PA组装和互连中的关键参数进行了仿真和优化。研制出450MHzCDMA手机LTCC功率放大器,增益29.0dB,VSWR为2.0∶1,PAE为34%,体积为6mm×6mm×1.2mm。