薄层SOS薄膜材料外延生长及其器件应用

亚微米 CMOS/ SOS器件发展对高质量的 1 0 0 - 2 0 0纳米厚度的薄层 SOS薄膜提出了更高的要求 .实验证实 :采用 CVD方法生长的原生 SOS薄膜的晶体质量可以通过固相外延工艺得到明显改进 .该工艺包括 :硅离子自注入和热退火 .X射线双晶衍射和器件电学测量表明 :多晶化的 SOS薄膜固相外延生长导致硅外延层晶体质量改进和载流子迁移率提高 .固相外延改进的薄层 SOS薄膜材料能够应用于先进的 CMOS电路 .     

硅衬底上异质外延生长硅化钴研究进展

综述近年国内外在CoSi2／Si异质外延生长技术领域的研究进展,在半导体衬底上异质外延具有优良导电特性的金属硅化物,从基础研究和技术发展两方面都具有重要价值。利用Co／Ti／Si多层薄膜固相反应实现CoSi2／Si异质外延,是近年取得重要进展的新方法。应用这种方法在（111）和（100）硅衬底上都可实现CoSi2外延生长,无需在超高真空下进行,与硅器件基本工艺相容性好,可形成自对准硅化物接触结构,对发展新器件制造技术有重要作用。在简要介绍分子束外延和离子合成CoSi2外延薄膜生长技术后,重点介绍和评述新型固相异质外延方法的工艺技术、机理和应用研究进展。     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

用于先进CMOS电路的150mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

双异质外延Si/Al2O3/Si薄膜制作的CMOS器件

报道了利用高真空MOCVD外延生长γ氧化铝的技术和利用SOS CMOS的成熟工艺制作双异质外延Si/γ-Al2O3/Si单晶薄膜以及用其研制Si/γ-Al2O3/Si CMOS场效应晶体管、Si/γ-Al2O3/Si CMOS集成电路的初步结果.     

分子束外延InAlSb/InSb晶体的质量研究

InAlSb/InSb薄膜材料的晶体质量会直接影响器件的性能。提高薄膜材料的晶体质量可以有效降低器件的暗电流,提高探测率和均匀性等。主要报道了掺铝锑化铟分子束外延技术的初步研究结果。通过采用多种测试方法对InAlSb分子束外延膜的晶体质量进行了分析,找出了影响晶体质量的因素,提高了InAlSb分子束外延的技术水平。实验结果表明,通过优化生长温度、束流比、升降温速率以及退火工艺等生长条件,可以获得高质量的InAlSb分子束外延膜。     

双异质外延Si/Al_2O_3/Si薄膜制作的CMOS器件

报道了利用高真空 MOCVD外延生长 γ氧化铝的技术和利用 SOS CMOS的成熟工艺制作双异质外延 Si/ γ-Al2 O3/ Si单晶薄膜以及用其研制 Si/ γ- Al2 O3/ Si CMOS场效应晶体管、Si/ γ- Al2 O3/ Si CMOS集成电路的初步结果     

双异质外延Si/Al2O3/Si薄膜制作的CMOS器件

报道了利用高真空MOCVD外延生长γ氧化铝的技术和利用SOS CMOS的成熟工艺制作双异质外延Si/γ-Al2O3/Si单晶薄膜以及用其研制Si/γ-Al2O3/Si CMOS场效应晶体管、Si/γ-Al2O3/Si CMOS集成电路的初步结果.     

利用改进的固相外延技术改善CMOS/SOS器件的特性

ＣＭＯＳ／ＳＯＳ器件同体硅ＣＭＯＳ器件相比,载流子迁移率较低,沟道漏电电流较大,它们主要是由异质外延硅膜缺陷,特别是靠近硅蓝宝石界面的硅膜缺陷造成的．本文描述一种改进的固相外延技术提高外延硅膜质量进而改善ＣＭＯＳ／ＳＯＳ器件特性的实验结果．     

Si衬底上Ge外延薄膜与器件研究进展

随着Si基器件发展遇到瓶颈,具有更优异性能且与Si基CMOS工艺良好兼容的Ge基器件展现出了应用于集成电子与光电子领域的广阔前景.然而,Si基Ge器件性能会受制于Si与Ge之间较大的晶格失配所产生的高密度位错.因此,控制Si衬底上Ge外延薄膜的位错密度成为高性能Ge器件制备的研究重点.文章着重介绍了插入层、低温成核层和选区外延生长技术3种Si衬底上Ge外延薄膜位错控制技术的基本原理及研究进展,讨论了Si基Ge器件的最新研究进展,并展望了Si基Ge薄膜生长和器件制备的发展前景.     

Thin-film silicon: Preparation, properties, and device applications

This paper will review the properties of thin silicon films deposited on sapphire (SOS) and magnesium aluminate spinel by the pyrolysis of silane in the temperature range 900-1200°C. Variations of carrier mobility, free-carrier concentration, minority carrier lifetime, crystalline perfection, and surface quality will be discussed as a function of substrate crystal and growth parameters. MOS transistors exhibiting field-effect mobility close to that obtained with bulk silicon have been fabricated and a complementary MOS transistor memory cell has been constructed with a WRITE-READ delay of 6 ns. The standby power for the cell is typically 10 µW. Other CMOS circuits display a pair-delay of 1.5-2.0 ns. AIl-epitaxial bipolar transistors with a current gain of 5 and fTof 350 MHz have been made in which all layers are sequentially deposited during one high-temperature operation. Recent improvements in bipolar fabrication techniques have lead to current gains as high as 25 at 10 mA.     

Growth and properties of high-quality very-thin SOS films

The increased emphasis on submicron geometry CMOS/SOS devices has created a need for high quality silicon-on-sapphire films with thicknesses of the order of 0.1 to 0.2 μm. To date the only viable way of producing high quality SOS films with these thicknesses has been through the application of recrystallization and regrowth techniques. The need for as-grown, high-quality, very-thin SOS films has prompted a study of film quality vs growth rate for films with thicknesses in the 0.1 to 0.2 μm range as a possible way of producing thin high-quality SOS films. It has been found that film quality increased as the growth rate increased. It was possible to produce films as thin as 0.1 μm with mobilities nearly as high as 1 μm films, if the film growth rate was higher than 4 μm/ min.     

横向固相外延生长及其影响因素的研究

对非超高真空条件下对在有ＳｉＯ２图形的硅单晶衬底上用离子束溅射沉积非晶硅薄膜，经过真空退火形成的横向固相外延生长及其影响因素进行了研究，得出了有利于Ｌ－ＳＰＥ生长的材料参数和工艺处理条件。     

薄膜亚微米CMOS／SOS工艺的开发及其器件的研制

本文较为详细地介绍了薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺技术的开发过程，薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺主要包括双固相外延，双层胶光刻形成亚微米细线条硅栅、Ｈ２－Ｏ２合成氧化薄栅氧化层以及快速退火等新的工艺技术，利用这套工艺成功地研制出了高性能薄膜来微米ＣＭＯＳ／ＳＯＳ器件和门延迟时间仅为１７７ｐｓ的１９级ＣＭＯＳ／ＳＯＳ环形振荡器，与厚膜器件相比，薄膜全耗尺器件和电路的性能得到了明显的提高。     

CMOS/SOS semi-static shift registers

Complementary metal-oxide-semiconductor (CMOS) technology has been combined with thin silicon on sapphire films (SOS) for the fabrication of shift registers designed for full TTL compatibility d.c. storage capability, 20 MHz operating frequency, single phase clock and data inputs, and double rail data outputs. Typical power dissipation levels were on the order of 500 nW per stage during standby and 250 /spl mu/W per stage when operating at 20 MHz.     

Performance of CMOS devices in silicon-on-sapphire films after solid-phase epitaxial growth with rapid electron-beam heating

The crystal quality of 0.3-µm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 10¹⁵ions/cm²at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistor mobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation.     

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0-μm-thick films have been fabricated on SOS films 0.2 μm thick that have been grown at growth rates above 4 μm/min     

Saddle add-on metallization for RF-IC technology

A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of /spl sim/13 for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate is demonstrated.     

VO2(B)薄膜的制备及特性优化研究

采用直流磁控溅射法,在纯氩气氛中溅射V2O5靶材,在覆盖有氮化硅薄膜的P(100)硅基片表面沉积氧化钒薄膜.对沉积的薄膜进行了后续高真空高温退火处理.利用XRD对薄膜的晶相进行了分析,结果表明退火处理前和退火处理后的薄膜都具有VO2各晶面的取向,XPS分析证明了XRD的物相分析结果.对薄膜的方阻特性的测试表明生成的薄膜是典型的VO2(B)薄膜,退火后的薄膜方阻减小,方阻温度系数也降低.在此基础上,利用薄膜晶界散射理论,通过改变薄膜沉积时间和沉积温度使薄膜的方阻和方阻温度系数随薄膜厚度和晶粒大小而变化,从而使薄膜的电性能达到优化.