A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

Motivated by the battery-operated applications that demand compact,lightweight andefficient DC-DC converters,many kinds of converter circuits have been published.Amongthem,resonantconverters and the soft-switching convertershave greatl...     

嵌入式开关电容DC-DC变换器的新颖控制技术

提出了一种针对单片集成开关电容DC-DC变换器进行优化的设计方案.阐述了开关电容DC-DC变换器电路的拓扑结构及其基本工作原理,给出了单片集成开关电容DC-DC变换器的等效电阻控制方法.考虑到集成工艺的兼容性问题,在电路设计时,用n沟MOSFET替代二极管;为了改善变换器的输出特性,在标准2μm p阱双层多晶硅单层金属CMOS工艺中增加了一次MOSFET阈值电压的调整步骤,实现了升压开关电容DC-DC变换器的单片集成.芯片面积为0.4mm2,测试结果显示,在变换器输入电压为3V,输出电压为5V,电路开关频率为9.8MHz时,输出功率为0.63mW,效率达到68%.     

一体化固态T/R组件前级电源设计

本文对基于隔离ZCS-Sepic-PFC变换器构成的一体化固态T/R组件前级电源的设计进行了描述。该变换器开关利用电感和电容谐振实现了零电流开关(ZCS),在高频化的同时降低了开关损耗,同时该变换器具有功率因数校正(PFC)的特性,适合应用于ac/dc电源中。文中对电路工作原理和功率因数校正的特性进行了详细分析,并给出组件前级电源的参数设计及电源部分工作波形。     

Monolithic millimeter-wave IMPATT oscillator and active antenna

A single-chip millimeter-wave transmitter module in which GaAs IMPATT diodes are monolithically integrated with a microstrip resonator and a loop antenna is discussed. Devices operating at 43.3 GHz produce 27-mW CW output power with 7.2% conversion efficiency. Radiation patterns of linear arrays of such radiating elements were determined as a function of interelement spacing and number of elements. The oscillator chip was also directly coupled to and power combined in waveguides, producing an inexpensive millimeter-wave source     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.     

一种80 MHz隔离式DC-DC变换器

介绍了一种80 MHz隔离式DC-DC变换器,无芯PCB变压器实现了VHF隔离,利用交叉耦合电路和无芯PCB变压器形成持续振荡,采用肖特基二极管作为整流器件,电压反馈环路保证整个系统能够稳定输出。采用FEM和EDA软件实现了无芯PCB变压器的设计和整体电路的仿真。测试结果表明,该变换器能够提供3.3 V隔离电压输出和0.3 W功率输出,效率约为43%。     

Low-power variable frequency PFC converters

Based on the SinoMOS 1 μm 40 V CMOS process, a novel power factor corrention (PFC) converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a pro-grammable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversion-mode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 μA, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor (PF) is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61×1.52 mm~2.     

Copper-based hybrid fabrication of a 50 W, 5 MHz 40 V-5 V DC/DCconverter

A prototype 50 W, 40 V to 5 V DC/DC converter operating at 5 MHz and constructed with chip and wire hybrid techniques on a ceramic substrate with copper thick-film conductors is presented. A brief discussion of the thick-film process is given to point out the special issues concerning copper-based conductor systems. Some of the specific trade-offs that arise with regard to the construction of a power circuit with hybrid techniques are discussed. A method by which transformers may be fabricated to have very little leakage inductance, both internally and in their connection to rectifiers, is then described. The performance of a power circuit, the dual resonant forward converter is presented     

1Gb/s CMOS调节型共源共栅光接收机

基于特许0.35μm EEPROM CMOS标准工艺设计了一种单片集成光接收机芯片,集成了双光电探测器(DPD)、调节型共源共栅(RGC)跨阻前置放大器(TIA)、三级限幅放大器(LA,limiting amplifier)和输出电路,其中RGCTIA能够隔离光电二极管的电容影响,并可以有效地扩展光接收机的带宽。测试结果表明,光接收机的3dB带宽为821MHz,在误码率为10-9、灵敏度为-11dBm的条件下,光接收机的数据传输速率达到了1Gb/s;在3.3V电压下工作,芯片的功耗为54mW。     

高性能PWM型DC-DC升压变换器研究

设计了一种单片集成PWM型电流模式升压变换器,芯片内部集成了耐压22V的DMOS功率开关管,开关频率为1.6MHz,采用1.5μmBCD工艺实现。芯片具有很宽的输入电压(2.7~14V)、高效率(85%)、低关断电流、快速暂态响应和低功耗等特性,适宜于用作便携式设备的电源管理,也可作为IP核,嵌入同种工艺下的其它芯片。文中除了对芯片设计方法、思路及主要电路模块结构的设计方案进行讨论外,还提出了减小单片集成开关电源噪声的措施。     

A monolithic transformer coupled 5-W silicon power amplifier with59% PAE at 0.9 GHz

This paper presents the circuit design and application of a monolithically integrated silicon radio-frequency power amplifier for 0.8-1 GHz. The chip is fabricated in a 25-GHz-f_T silicon bipolar production technology (Siemens B6HF). A maximum output power of 5 W and maximum efficiency of 59% is achieved. The chip is operating from 2.5 to 4.5 V. The linear gain is 36 dB. The balanced two-stage circuit design is based fundamentally on three on-chip transformers. The driver stage and the output stage are connected in common-emitter configuration. The input signal can be applied balanced or single-ended if one input terminal is grounded. One transformer at the input acts as balun as well as input matching network. Two transformers acts as interstage matching network     

A New PWM-Controlled Quasi-Resonant Converter for a High Efficiency PDP Sustaining Power Module

A new pulsewidth modulation (PWM)-controlled quasi-resonant converter for a high-efficiency plasma display panel (PDP) sustaining power module is proposed in this paper. The load regulation of the proposed converter can be achieved by controlling the ripple of the resonant voltage across the primary resonant capacitor with a bidirectional auxiliary circuit, while the main switches are operating at a fixed duty ratio and fixed switching frequency. Hence, the waveforms of the currents can be expected to be optimized from the view-point of conduction loss. Furthermore, the proposed converter has good zero-voltage switching (ZVS) capability, simple control circuits, no hign-voltage ringing problem of rectifier diodes, no dc offset of the magnetizing current and low-voltage stresses of power switches. Thus, the proposed converter shows higher efficiency than that of a half-bridge LLC resonant converter under light load condition. Although it shows the lower efficiency at heavy load, because of the increased power loss in auxiliary circuit, it still shows the high efficiency around 94%. In this paper, operational principles, features of the proposed converter, and analysis and design considerations are presented. Experimental results demonstrate that the output voltage can be controlled well by the auxiliary circuit using the PWM method.      

A 622 Mb/s monolithically integrated InGaAs/InP four-channel p-i-nFET receiver array

The authors describe the sensitivity and crosstalk characteristics of a long-wavelength monolithically integrated four-channel photoreceiver array. This receiver consists of 4 p-i-n PDs, 24 JFETs, and 28 level-shift diodes. The device is fabricated using MOVPE-grown crystals and a Be ion implantation technique. The receiver chip demonstrates a sensitivity of between -30.6 and -31.4 dBm, and crosstalk below -20 dB over its operating frequency range. Sensitivity deterioration due to crosstalk is demonstrated and is shown to be a critical factor in system performance. The crosstalk is mainly due to parasitic inductances on the external power supply circuits     

一种片内集成飞电容的自适应开关电容DC-DC

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波＜40 mV     

A single-stage power-factor-corrected AC/DC converter

This paper presents a single-stage isolated converter topology designed to achieve a regulated DC output voltage having no low-frequency components and a high-input power factor. The topology is derived from the basic two-switch forward converter, but incorporates an additional transformer winding, inductor and a few diodes. The proposed circuit inherently forces the input current to be discontinuous and AC modulated to achieve high-input power factor. The converter output is operated in discontinuous mode to minimize the bulk capacitor voltage variations when the output load is varied. Analysis of the converter is presented, and performance characteristics are given. Design guidelines to select critical components of the circuit are presented. Experimental results on a 150 W 50 kHz universal input (90-265 V) 54.75 V output AC/DC converter are given which confirm the predicted performance of the proposed topology     

PWM半桥变换器电路仿真

随着电力电子技术的迅速发展,PWM型DC-DC变换器的应用日益广泛。如今,高性能、高效率、小型化和轻量化越来越成为各类DC-DC变换器追求的目标。文中优选电路结构简单、容易控制的半桥电路作为直直变换拓扑,在剖析了脉宽调制对称半桥变换器工作原理及特性后,设计出270 V直流输入、360 V直流输出、输出功率为500 W变换器的相关参数。切实了解SG1525芯片脉冲产生原理后,设计出控制电路参数,从而搭建出完整的闭环系统。详尽分析了所得出仿真结果,并以此验证了理论分析和工程设计的正确性。     

紧凑型Ka波段PHEMT微波单片集成VCO

设计并流片制作了基于GaAs PHEMT工艺的Ka波段微波单片集成压控振荡器(MMIC VCO).该VCO具有紧凑、宽电调谐带宽及高输出功率的特点.提出了缩小芯片面积及增大调谐带宽的方法,同时还给出了设计MMIC VCO的基本步骤.该方法设计并流片制做的MMIC VCO的测量结果为:振荡频率为36±1.2GHz,输出功率为10士1dBm,芯片面积为1.3mm×1.0mm.     

An Analysis of the ZVS Two-Inductor Boost Converter under Variable Frequency Operation

The two-inductor boost converter has been previously presented in a zero-voltage switching (ZVS) form where the transformer leakage inductance and the MOSFET output capacitance can be utilized as part of the resonant elements. In many applications, such as maximum power point tracking (MPPT) in grid interactive photovoltaic systems, the resonant two-inductor boost converter is required to operate with variable input output voltage ratios. This paper studies the variable frequency operation of the ZVS two-inductor boost converter to secure an adjustable output voltage range while maintaining the resonant switching transitions. The design method of the resonant converter is thoroughly investigated and explicit control functions relating the circuit timing factors and the voltage gain for a 200-W converter are established. The converter has an input voltage of 20V and is able to produce a variable output voltage from 169V to 340V while retaining ZVS with a frequency variation of 1MHz to 407kHz. Five sets of theoretical, simulation and experimental waveforms are provided for the selected operating points over the variable load range at the end of the paper and they agree reasonably well. The converter has achieved part load efficiencies above 92% and an efficiency of 89.6% at the maximum power of 200W     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset