Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses

Several complex electrostatic discharge (ESD) failure mechanisms have been found in the interface circuits of an IC product with multiple separated power domains. In this case, the machine-model (MM) ESD robustness cannot achieve 150 V in this IC product with separated power domains, although it can pass the 2-kV human-body-model (HBM) ESD test. The negative-to-VDD (ND) mode MM ESD currents were discharged by circuitous current paths through interface circuits to cause the gate oxide damage, the junction filament, and the contact destruction of the internal transistors. The detailed discharging paths of ND-mode ESD failures were analyzed in this paper. In addition, some ESD protection designs have been illustrated and reviewed to further comprehend the protection strategies for cross-power-domain ESD events. Moreover, one new active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13- $muhbox{m}$ CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.      

A Case Study of Problems in JEDEC HBM ESD Test Standard

There is a current need for modification of EIA/JEDEC Human-Body model (HBM) electrostatic discharge (ESD) test standard, which does not define start and step test voltages. In the current standard, some measurements start at several kilovolts, which ignore the fact that ESD protection devices may fail under low voltage stresses. In this paper, a grounded-gate structure with an n-well ballast resistor connecting its drain and PAD is investigated for HBM ESD sustaining levels. When tested with a Zapmaster starting from 1 kV, the withstand voltage exceeds 8 kV, whereas the structure failed at 350 V when the test starts from 50 V. The test results from a transmission-line-pulsing system validate the phenomenon. The reason for the failure is also studied and confirmed with optical-beam-induced resistor change system failure analysis results. To address this general issue, a suggestion for improving the present HBM ESD testing standards for industry applications is made.      

900 MHZ radio‐frequency identification rectifier with optimization and reusing of electro‐static discharges protections in 180 nm digital CMOS technology

Sensitivity and electro‐static discharges (ESD) protection level are crucial parameters for any Ultra High‐Frequency (UHF) power rectifier–harvester designed for radio‐frequency identification (RFID) devices. While sensitivity limits the reading range of the interrogator‐to‐tag communication link, the requirement for an adequate protection against ESD is enforced in commercial devices connected to a printed antenna. Both resistive and capacitive parasitics of the protection circuits severely affect RF performance of the device. In the paper, a rectifier for UHF RFID embedding an ESD protection for 2 kV human‐body discharge model (HBM) level is proposed. The target of a low added parasitic capacitance is achieved by adapting the protection circuit to the RFID rectifier and reusing the ESD clamp for additional functions being mandatory in a UHF RFID front end. The layout of the ESD clamp has been optimized for minimum parasitic resistance without sacrificing the protection level. Two UHF harvesters were implemented in a 180 nm digital complementary metal‐oxide semiconductor (CMOS) technology, featuring a minimum sensitivity of ?15.5 dBm with an ESD protection level of 2 kV HBM. Copyright © 2014 John Wiley & Sons, Ltd.     

考虑寄生参数影响的芯片RC-HBM静电测试模型

采用常规的人体模型(Human Body Model, HBM)进行静电释放(Electro-Static Discharge, ESD)测试时往往容易受到寄生参数的影响,使得电源芯片抗静电能力测量值与实际抗静电能力存在偏差,导致劣质产品通过HBM ESD测试,影响电源芯片产品良品率的提升。为此,提出了一种RC-HBM模型,通过引入RC并联支路,校正因寄生参数引起的静电放电电流的偏差,满足电源芯片静电可靠性测试的要求。首先阐述了静电对电源芯片的损坏机理。其次,分析了寄生参数对ESD电流的影响,阐述了常规HBM ESD测试的局限性。并提出了一种新型的RC-HBM模型,给出了RC并联支路参数的设计依据。最后,通过批量实验验证了所提RC-HBM模型的准确性和合理性。     

Analysis of soft breakdown failure with ESD on output buffernMOSFETs and its improvement

The leakage increase of the off-state MOSFETs after an ESD event has been studied for output transistors with the thin gate oxide and LDD structures. Leakage increase called “soft breakdown” has been found at relatively low ESD testing voltages (200-300 V). This soft breakdown is caused by the creation of interface traps due to the snap-back stressing during the ESD event. The creation of interface traps has enhanced the interface trap to band tunneling current at the drain side of the MOSFETs. The improvement of the ESD threshold has also been proposed with an additional arsenic implantation into the n^$ region. It has been confirmed that the arsenic implantation improved the HBM ESD threshold to more than 2000 V     

Human-Body-Model Electrostatic-Discharge and Electrical-Overstress Studies of Buried-Heterostructure Semiconductor Lasers

Optoelectronic components such as laser diodes, light-emitting diodes, and photodiodes are susceptible to electrostatic discharge (ESD) and electrical overstress (EOS). Human-body model (HBM) is the most widely adopted method for the characterization of the ESD performance. In this paper, we report a comprehensive study of the ESD and EOS characteristics of buried-heterostructure (BH) semiconductor lasers using the HBM. Threshold current, optical power, optical spectrum, and reverse-bias current are characterized during the ESD study. We show that the ESD-failure thresholds depend upon the polarity. The chip can sustain the highest ESD stress under forward bias and the lowest one under forward/reverse bias. We also show that the BH lasers exhibit two types of ESD-degradation behavior. The soft degradation is characterized by a gradual increase in the threshold current, whereas the hard degradation is identified by a sudden jump in the threshold current during the ESD voltage ramp. The ESD-degradation behavior seems to be influenced by the cavity length. The failure-analysis results show that about 27% of the ESD failure is related to facet damage. The damage regions occur at the upper laser mesa structure and form preferentially on the bond-pad side. The preferential formation of the facet damage is suggestive of current-crowding effect. We have also found that the ESD-degradation behavior is a function of the facet damage. The soft-degradation failure shows a stronger correlation with the facet damage than the hard-degradation one. Finally, we demonstrate that the ESD performance of the laser can be improved by adding a protection diode.     

Investigation of the gate-driven effect and substrate-triggeredeffect on ESD robustness of CMOS devices

The gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD) robustness of CMOS devices are measured and compared in this paper. The operation principles of gate-grounded design, gate-driven design, and substrate-triggered design on CMOS devices for ESD protection are explained clearly by energy-band diagrams. The relations between ESD robustness and the devices with different triggered methods are also explained by transmission line pulsing (TLP) measured results and energy-band diagrams. The turn-on mechanisms of nMOS devices with triggered methods are further verified using the emission microscope (EMMI) photographs of the nMOS devices under current stress. The experimental results confirm that the substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices better than the gate-driven design. The human body model (HBM) ESD level of nMOS with a W/L of 400 μm/0.8 μm in a silicided CMOS process can be improved from the original 3.5 kV to over 8 kV by using the substrate-triggered design. The gate-driven design cannot continually improve the ESD level of the device in the same deep-submicron CMOS process     

静电放电和方波EMP对微电子器件的效应

为了得到微波低噪声晶体管电磁脉冲的最灵敏端对和最敏感参数以及相关规律和器件的损伤/失效机理和模式,首先采用静电放电人体模型(HBM),针对两类硅晶体三极管(3DG218、3358)进行了静电放电敏感性相关实验,得到该类晶体管的ESD敏感端对是CB结;器件损伤时的灵敏参数是VBRCEO;又采用方波注入法对两晶体管进行实验比较了从CB结反向注入与从EB结反向注入的损伤电压值,发现该类器件的EMP最敏感端对是CB结而非以往人们认为的EB结。     

工业ESD模拟设备波形校准及校准实例

本文阐述了如何根据业界相应的标准对ESD模拟装置进行波形校准,先给出了工业进行ESD测试的背景,然后简要介绍了一种较为常见的ESD静放电形式——HBM(人体放电模式)——产生以及其在工业中进行波形校准的基本原理和所需设备,并对如何正确架设调整校准设备,如何进行有关静放电模拟器和测量板的校准程序进行了探讨,最后以HBM 1 kV短路波形校准为实例进行了更进一步的说明.结果表明通过架设校准电路以及设定正确的波形校准程序,同时以业界的明确的标准为规范,相关技术人员就可以对ESD模拟设备产生的静放电波形进行校准.     

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

A new electrostatic discharge (ESD) protection structure of high-voltage p-type silicon-controlled rectifier (HVPSCR) that is embedded into a high-voltage p-channel MOS (HVPMOS) device is proposed to greatly improve the ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional n+ diffusion into the drain region of HVPMOS, the transmission-line-pulsing-measured secondary breakdown current of the output driver has been greatly improved to be greater than 6 A in a 0.5- mum high-voltage complementary MOS process. Such ESD-enhanced VFD driver IC, which can sustain human-body-model ESD stress of up to 8 kV, has been in mass production for automotive applications in cars without the latchup problem. Moreover, with device widths of 500, 600, and 800 mum, the machine-model ESD levels of the HVPSCR are as high as 1100,1300, and 1900 V, respectively.     

ESD脉冲对集成电路损伤效应的实验研究

为了研究复杂波形脉冲对集成电路的损伤效应,用改变ESD模拟器放电参数产生的不同的静电放电脉冲对某集成电路芯片进行了注入损伤效应实验。给出了各主要的损伤参数与放电电压的散点图,并借助曲线拟合的方法进行了分析。结果表明:IC芯片注入通路上的电阻在脉冲波形发生变化时变化不大,电流随放电电压增大;芯片上的峰值功率及峰值能量与放电电压满足P(W)=AUBD。最后,比较了各脉冲注入下器件的主要参数损伤阈值,得到结论:ESD模拟器放电参数改变对器件损伤阈值大小的影响在1~2倍间,相同参数在不同注入脉冲下的阈值处于同数量级。     

Modeling ESD protection

This work presents the modeling and simulation of ESD circuit design protection. The electrostatic discharge (ESD) is a charge rebalancing process between two adjacent ICs. The ESD can cause IC failure during the manufacturing, the testing, the handling and the assembly of integrated circuits (ICs). ESD protection design methodology needs to be as systematic and transferable as possible. The empirical, trial and error method for creating ESD protection schemes is based on fabricating several test protection structures, gradually applying increasing voltage pulses and then measuring the functionality of the protection structures. This method is time consuming and destructive in nature. The model could be used to optimize the ESD circuit's design and predict its protection performance. A combination of bias conditions and layout parameters could maximize the ESD robustness device. This optimization can be achieved by developing simulation tools for ESD circuits. ESD is a phenomenon that causes reliability problems and even permanent damages to the IC since the goal is to find the voltage and the current limits before the device fails permanently.     

ESD failure mechanisms of analog I/O cells in 0.18-/spl mu/m CMOS technology

Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-/spl mu/m 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-/spl mu/m CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.     

Filter optimization for X-ray inspection of surface-mounted ICs

A thin Zn filter (/spl sim/300 /spl mu/m) and relatively low X-ray tube voltage (/spl sim/45 kV) is recommended for X-ray inspection of surface-mounted device solder joints on printed wiring boards (PWBs). An optimal filter minimizes the Si dose that could result in cumulative damage to sensitive integrated circuit (IC) nodes, yet provides good contrast for metals such as Cu traces on PWBs and device solder balls. While we expect orders of magnitude Si dose reductions when effective filters are inserted, a properly chosen filter should not attenuate the portion of the white X-ray spectrum required to image Cu, Sn, and Pb (solder balls). Some X-ray inspection suppliers can achieve a Si dose of as little as 0.060 rads, while other X-ray inspection suppliers, not yet optimized for minimum dose, may use as much as four orders of magnitude more dose. We used thermo luminescent detectors (TLDs) to measure the X-ray dose that IC product shipments would encounter during a shipping process, for example, as personal baggage or cargo, as /spl les/0.050 rads.     

A New Flip-Flop-Based Transient Power Supply Clamp for ESD Protection

As CMOS technology is scaled, the design of a robust electrostatic-discharge (ESD) protection circuit that is transparent to the main circuit is becoming more challenging. For high- frequency applications where minimum parasitic capacitance is required, diodes along with clamps are a popular ESD protection method. The main challenge in the clamp design is to keep the clamp in "on" mode for the whole ESD event while minimizing area and avoiding false triggering. In this paper, a new clamp that uses a flip-flop to turn on the clamp for the complete ESD event is presented. The trigger circuit is able to keep the clamp on for over 2 mus, and this clamp passes a 3-kV HBM ESD stress. Simulation results show that this clamp is immune to false triggering and power supply noise. Furthermore, the stability problem in clamps is addressed, and the new clamp is shown to be immune to oscillation.     

Investigation on Board-Level CDM ESD Issue in IC Products

The impacts caused by board-level charged-device-model (CDM) electrostatic-discharge (ESD) events on integrated-circuit products are investigated in this paper. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment is performed to investigate the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs), charged voltages, and series resistances in the discharging path. Experimental results show that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, the chip- and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The test results show that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level of the test circuit, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure in the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test.      

ESD的物理失效分析及放电路径的研究

本文将IC电过力失效机理划分为EOS和ESD分别进行阐述,EOS和ESD2种失效模式的相似使得对它们失效机理的判断变得困难,但借助SEM和FIB等先进的成像设备可以揭示2种失效机理的重要差别.本文先通过实例分析揭示了2种失效机理的差别,其中从理论角度突出对ESD失效机理和失效位置的研究;然后,借助仪器分析的结果对ESD失效案例的ESD放电路径做了合理推断,这种通过失效分析推断放电路径的方法对于改善ESD保护电路性能和提高ESD防护等级有着重要参考作用.     

Human body model ESD simulation including self heating effect

The human body model (HBM) ESD simulation is presented. The tempereature rise owing to self heating can be dealt with in a simple manner ignoring heat conduction, since ESD phenomenon is faster than heat conduction. Transient I _d -V _d trajectories and the temperature rise due to ESD are successfully simulated.     

Analysis of the charge/discharge processes for the basic ESD models

The human body model (HBM), charged device model (CDM) and field induced model (FIM) have been developed to simulate the electrostatic discharge (ESD) event. The charge/discharge processes for these models are analyzed using Maxwell's technique and a sphere model. Body potentials, energies and the charge transfer during a discharge are calculated as functions of the charge on the source conductor and the capacitance coefficients for the conductors used. Approximate solutions for the HBM are proposed, and measurements made using a system of conductors and a ground plane are used to determine the accuracy of these solutions. Discrepancies between experimental and theoretical results are analyzed using system potential sensitivity factors     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.