Efficient Implementations for AES Encryption and Decryption

This paper proposes two efficient architectures for hardware implementation of the Advanced Encryption Standard (AES) algorithm. The composite field arithmetic for implementing SubBytes (S-box) and InvSubBytes (Inverse S-box) transformations investigated by several authors is used as the basis for deriving the proposed architectures. The first architecture for encryption is based on optimized S-box followed by bit-wise implementation of MixColumns and AddRoundKey and optimized Inverse S-box followed by bit-wise implementation of InvMixColumns and AddMixRoundKey for decryption. The proposed S-box and Inverse S-box used in this architecture are designed as a cascade of three blocks. In the second proposed architecture, the block III of the proposed S-box is combined with the MixColumns and AddRoundKey transformations forming an integrated unit for encryption. An integrated unit for decryption combining the block III of the proposed InvSubBytes with InvMixColumns and AddMixRoundKey is formed on similar lines. The delays of the proposed architectures for VLSI implementation are found to be the shortest compared to the state-of-the-art implementations of AES operating in non-feedback mode. Iterative and fully unrolled sub-pipelined designs including key schedule are implemented using FPGA and ASIC. The proposed designs are efficient in terms of Kgates/Giga-bits per second ratio compared with few recent state-of-the-art ASIC (0.18-μm CMOS standard cell) based designs and throughput per area (TPA) for FPGA implementations.     

面向HT的CCMP算法的面积优化实现方法

根据802.11i AES加密/解密算法的要求,配合给定的系统时钟频率,提出了较为节约面积的、极为规则的AES运算电路的实现方法.通过分析系统时钟与系统数据吞吐量的要求,给出了较为合理的面向HT(High Throughput)的802.11i CCMP AES算法系统架构,对其中的AES运算单元的实现方法进行分析比较,得出了较小面积的AES运算单元的实现方案.用Design Compiler做综合分析后发现,优化后的面积比现有的方法至少下降了31%,从而有效地降低了IC的成本.     

High Definition Image Encryption Algorithm Based on AES Modification

In this article, a high-speed and highly restricted encryption algorithm is proposed to cipher high-definition (HD) images based on the modified advanced encryption standard (AES) algorithm. AES is a well-known block cipher algorithm and has several advantages, such as high-level security and implementation ability. However, AES has some drawbacks, including high computation costs, pattern appearance, and high hardware requirements. The aforementioned problems become more complex when the AES algorithm ciphers an image, especially HD images. Three modifications are proposed in this paper to improve AES algorithm performance through, decreasing the computation costs, decreasing the hardware requirements, and increasing the security level. First, modification was conducted using MixColumn transformation in 5 rounds instead of 10 rounds in the original AES-128 to decrease the encryption time. Security is enhanced by improving the key schedule operation by adding MixColumn transformation to this operation as second modification. In addition, to decrease the hardware requirements, S-box and Inv. S-box in the original AES are replaced by one simple S-box used for encryption and decryption in the proposed method. The proposed AES version conducts one of the ciphering modes to solve the appearance pattern problem. Experimental results indicate that the proposed modifications to the AES algorithm made the algorithm more compatible with HD image encryption.     

一种AES密码算法的硬件实现

介绍了一种适用于较小面积应用场合AES密码算法的实现方案。结合该算法的特点,在常规轮变换中提出一种加/解密列混合变换集成化的硬件结构设计,通过选择使用同一个模块,可以实现加密和解密中的线性变换,既整合了部分加/解密硬件结构,又节约了大量的硬件资源。仿真与综合结果表明,加/解密运算模块面积不超过25000个等效门,有效地减小了硬件实现面积,同时该设计方案也满足实际应用性能的需求。     

基于低成本FPGA的AES密码算法设计

主要介绍在逻辑资源少的现场可编程门阵列（FPGA）上实现高级数据加密标准（AES）算法设计。首先描述了AES加密算法,并在FPGA上优化实现AES算法,设计结构采用多轮加密共用一个轮运算的顺序结构,加密和解密模块共用密钥扩展模块,减少资源占用,在低时钟频率下保持较高的性能。采用了16位的并行总线通信接口,利用先进先出缓冲器（FIFO）对输入输出数据进行缓存。最后通过仿真和实测表明,在50MHz时钟下加解密速率可达530Mb/s。     

AES与ECC混合加密算法的无线数据通信系统设计

提出了一种新的无线数据通信数据加密算法。该算法利用高级加密标准AES加密数据，以ECC加密AES算法的密钥，并用ECC实现数字签名，无线数据系统的接收端对接收的信息进行相应的数据解密，得到原始数据。这样既能快速地进行数据加解密，又能很好地解决密钥分配问题，同时也能完成数字签名与验证功能，具有需求存储空间小、运算速度快、带宽需求低、密钥管理方便等优点，非常适合于无线通信网络环境下的数据加解密通信。     

AES加密算法在AP中的设计和实现

随着无线局域网(WLAN)的发展,其信息的安全也越来越受重视.AES作为无线局域网通信协议的核心加密算法,如何用硬件实现并应用在通信产品中尤为重要.文中在概述了AES(高级加密标准)算法基本原理的基础上,以FPGA为硬件平台,Altera公司的Quartus Ⅱ为工具,设计了AES加密算法在Ap(Access Point)中的硬件实现.实现了AES加密解密电路的顺序循环方式和两级流水线方式设计,并对这两种实现方式进行了比较.结果表明采用流水线方式设计虽然增加了资源消耗,但是明显的提高了速度.     

AES的小面积实现

论文简要介绍了新的高级加密标准AES算法(Rijndael)的加密解密流程,给出了AES的IP核实现,重点分析了小面积实现的关键。这种设计占用资源少,适合对速度要求不高的低端加密芯片。     

一种高效的彩色图像加密和解密算法

分析了基于Amold变换的加密方案在加密效果及加密效率方面的不足。提出了一种新的彩色图像加密及解密算法。加密过程将像素的物理位置置乱并映射到不同的色彩空间;解密过程提出了一种针对彩色图像的逆变换算法,使解密的时间仅依赖加密的密钥而不依赖变换周期。仿真分析比较了该算法在加密效果及加密效率方面的优势。实验数据表明,该加密算法的加密效果理想,且加密效率较高,是一种简单、可行的彩色图像加密方法。     

基于增强型延时感知CSE算法的AES S盒电路优化设计

针对高级加密标准（AES）S-盒优化,提出了一种增强型延时感知公共项消除（CSE）算法.该算法能够在不同延时约束条件下优化多常数乘法运算电路,并给出从最小延时到最小面积全范围的面积-延时设计折中.采用该算法优化了基于冗余有限域算术的S盒实现电路,确定了延时最优、面积最优的两种S盒构造.实例优化结果表明所提出算法的优化效率高、优化结果整体延时小.所设计的S盒电路基于65nm CMOS工艺库综合,结果表明,对比于已有文献中S盒复合域实现电路,所提出面积最优S盒电路的面积-延时积最小,比目前最小面积与最短延时的S盒组合逻辑分别减少了17.58%和19.74%.     

基于FPGA的AES算法的实现

介绍了高级加密标准( AES,Advanced Encryption Standard)算法的原理,设计了一个能够实现初始密钥128位、192位和256位可选的AES加解密算法系统,以适应多种使用环境.实验结果表明了基于现场可编程门阵列(FPGA)可编程逻辑器件的实现方法提供了并行处理能力,达到设计所要求的处理性能基准.整个设计具有很强的实用性,运行稳定,且效果良好,可以被广泛应用于网络,文件等安全系统.     

基于AHB总线的AES密码协处理器实现

AES加密算法是一种的常规加密算法,其被广泛应用在商业和政府部门。本文研究了AES(Advanced Encryption Standard)算法,包括AES的具体加密、解密过程以及基于AMBA(高级微控制器总线架构)总线的硬件实现方法。本文还介绍了一种用仿真与采用Xilinx公司的Virtex-4 LX100 FPGA器件来快速验证AES算法硬件IP核的方法。     

基于AES和RSA的加密信息传送方案

AES私钥密码体制加解密效率高，但在密钥管理方面比较困难，而RSA公钥密码体制不存在密钥管理的问题，但是加解密效率很低。根据这两种密码体制的优缺点，提出了基于AES和RSA的加密信息传送方案。此方案不但改善了RSA加解密的速度慢的缺点，也解决了AES体制申密钥管理因难的问题。     

基于矢量分解和相位剪切的非对称光学图像加密

结合矢量分解和相位剪切提出一种新的非对称光学图像加密算法,明文经过4个密钥加密得到分布均匀的密文和3个解密密钥。解密密钥在加密过程中产生,不同于加密密钥,实现了非对称加密,增加了系统的安全性。在矢量分解过程中产生的解密密钥与明文关联强,比现有光学非对称加密算法中明文对密文和解密密钥更为敏感,抵御选择明文攻击能力更强,同时也提高了解密密钥的敏感性。相位剪切的引入扩大了密钥空间,增强算法安全性,产生实数密文更便于传输。实验分析表明:该算法密文分布均匀、相邻像素相关性低,解密密钥、明文对解密密钥和密文敏感性高,抵御各种攻击能力强,有更好光学图像加密效果。     

A technique for the design of systolic arrays with bit-level pipelining

This paper describes a method for designing systolic structures with bit-level pipelining. The proposed technique starts with the signal flow graph representation of a given algorithm. A new signal flow graph rule, called the gain transfer rule is introduced to achieve bit-level pipelining. Using this approach, systolic arrays with bit-level pipelining are derived for a general recursive digital filter and a convolver. The proposed technique is quite general and has also been applied to obtain systolic structures for other problems such as vector transformation. In comparison with some previously reported designs, the new architectures are characterized by simpler basic processing cells and faster data throughput rate or smaller chip area requirements.The work of the first two authors was supported by an NRC Resident Research Associateship.     

Rijndael FPGA Implementations Utilising Look-Up Tables

This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.     

一种基于交替密钥的分组结构彩色图像加密算法

基于循环迭代的加/解密机制,提出了一种新的彩色图像加密算法。该算法在彩色空间应用了仿射变换,将交替密钥生成算法与分组结构引入到彩色图像加密过程,采用二种混沌映射对彩色图像加密,在每一次交替加密过程中,通过对初始密钥循环移位生成相应的交替密钥并产生二种子密钥,用于二种混沌映射,从而增加了密钥空间,有效提高了彩色图像加密算法的安全性。实验结果表明,该彩色图像加密算法安全性好,免疫性强,效率高。     

A novel error correction and encryption algorithm combined fountain code and AES

Satellite broadcast communications make demand on reliable and secure data transmissions. Aiming at balancing data disorder and correlation from encryption and errors correction, this paper proposes a novel error correction and encryption algorithm combined fountain code and advanced encrypt standard (FC‐AES), which constructs a 3‐layer cascade framework for cryptosystem to harmonize the coding payloads of services, products, and users. Furtherly, distributed degree would be compensated with round key, which provides with entire security controls. Information degree is designed to limit data overhead and disorder. Sparsely coding control for product degree is developed to prevent decoding error avalanche. We also provide a suitable decryption scheme for FC‐AES. The simulations show the new algorithm enhances the performance of data‐recovery failure probability by 29.56% and average error symbol rate by 13.09%.     

GPON中的AES加密

文章简单的介绍了GPON的体系结构与下行帧的结构,并着重介绍了AES加密的流程、方法与具体算法,最后对GPON中的AES加密、解密方法及AES计数器模式在GPON中的使用进行了详细的介绍。     

DWB-AES:基于AES的动态白盒实现方法

物联网设备因资源受限,需要兼具安全性、灵活性的轻量级密码模块保障安全,白盒密码能够满足物联网设备的安全需求.在常见的白盒密码实现方法中,往往密钥和查找表是绑定的,因此每次更换密钥都需要重新生成并更换查找表,这在实际应用中不够灵活.为了解决该问题,提出了一种基于AES的动态白盒实现方法,即DWB-AES.该方法通过改变轮...