铜线键合的抗氧化技术研究

在铜线键合的过程中通入惰性保护气体,或在纯铜线表面涂覆金属钯防氧化层都可以改善铜线键合的抗氧化性能。为了评价上述两种方法对铜线键合抗氧化性能的改进情况,使用先进的材料表征方法分析不同保护气体流量情况下键合形成的金属熔球的形貌,金属熔球表面的氧原子数分数和表面氧化层的厚度。研究表明,保护气体流量为0.51 L/min时,可以在保证成本较低的情况下获得最佳的抗氧化效果。通过XPS和TEM分析发现,铜线表面涂覆金属钯可以延长铜线的存储寿命,降低键合界面的氧含量,提高键合的可靠性。     

铜线键合技术的发展与挑战

铜线键合技术近年来发展迅速,超细间距引线键合是目前铜线键合的主要发展趋势.介绍了铜线键合的防氧化措施以及键合参数的优化,并从IMC生长及焊盘铝挤出方面阐述了铜线键合的可靠性机理.针对铜线在超细间距引线键合中面临的问题,介绍了可解决这些问题的镀钯铜线的性能,并阐述了铜线的成弧能力及面临的挑战.     

镀钯铜丝芯片键合工艺控制和可靠性研究

随着金价的不断上升,集成电路封装成本越来越高。为此,集成电路封装厂商纷纷推出铜线键合来取代金丝键合,以缓解封装成本压力。但是纯铜丝非常容易氧化,为了提高键合生产效率及产品可靠性,目前封装厂商主要采用镀钯铜丝作为键合丝。对集成电路镀钯铜丝键合生产技术和工艺控制方法进行了探讨,并和金丝及纯铜丝工艺控制进行了比较分析。对镀钯铜丝键合工艺主要失效模式进行了介绍和说明,并就弹坑检测试验方法进行了比较分析和总结。特别是对特殊产品的弹坑检测试验如何才能确保结果准确,进行了实例分析。     

铜线键合塑封器件破坏性物理分析技术

铜线替代传统的金线键合已经成为半导体封装工艺发展的必然趋势,因其材料和制造工艺的特点,其破坏性物理分析方法不同于金线或铝线键合的器件。提出铜丝键合塑封器件破坏性物理分析的步骤及判据参照标准,讨论了器件激光开封技术的工艺步骤和参数值以及键合强度测试判据和典型断裂模式,以解决铜线键合塑封器件的破坏性物理分析问题。     

铜丝球焊工艺在low-k芯片材料上实现可靠焊接性能的研究

为降低成本和应对芯片工艺的发展,本文针对铜线在low-K芯片材料上应用所面临的挑战,进行了研究和分析,从原理和方法上对影响铜线键合的关键因素,如自由球,保护气,压力和超声进行了描述,阐明了为防止芯片出现裂纹或者弹坑的应对方法,以及提高铜线可靠性的遵循原则,使得铜线可以大量代替目前的金线焊接工艺,在基板集成电路芯片上获得...     

芯片铝焊盘上不同金属丝键合质量研究

金属键合丝是半导体封装中非常关键的材料,它直接影响到键合的工艺表现和互连的可靠性。以不同金属丝(金丝、钯铜丝、金钯铜丝、银丝)和芯片铝焊盘第一焊点的键合为研究对象,分析对比各金属丝作为键合丝材料本身的基本性质、与铝焊盘键合第一焊点的工艺性能、与铝焊盘键合第一焊点的可靠性,发现其工艺性能和可靠性都满足半导体封装的键合要求。可靠性试验显示,各金属丝与铝焊盘之间的金属间化合物生长速度不同,但与可靠性失效无直接关系;可靠性失效都是由于金属丝焊球与铝焊盘脱落造成的;选择不同金属丝键合可满足不同的可靠性要求。     

分立器件铜线的键合特点及其工艺研究

对铜线键合的优缺点及分立器件的结构特点进行了具体分析。根据分析结果,并结合具体的实验,给出了键合工艺条件和工艺参数对分立器件铜线键合过程的影响。此研究对提高分立器件铜线键合产品的质量及可靠性具有重要意义。     

化学镍金基板焊点的失效分析

硅麦克风在消费类电子产品中成功应用,近年来得到了迅猛发展。硅麦克风的封装工艺由于MEMS的特殊结构和封装材料的特殊性,与常见IC封装有许多不同点。其中引线键合工序由于所使用的PCB基板材料特殊的加工工艺,使得引线在PCB基板上的焊点失效成为研究硅麦克风封装成品率和可靠性的一个重要课题。文章重点探讨了硅麦克风封装过程中引线键合工序焊点失效问题,通过不同金线键合方式和金线键合参数的分析,确立了适合于硅麦克风封装的金线键合工艺。     

铜线键合优势和工艺的优化

半导体封装对于芯片来说是必须的,也是至关重要的.封装可以指安装半导体集成电路芯片用的外壳,它不仅起着保护芯片和增强导热性能的作用,而且还起到沟通芯片内部世界与外部电路桥梁和规格通用功能的作用.文章阐述了铜线键合替代金线的优势,包括更低的成本、更低的电阻率、更慢的金属问渗透.再通过铜线的挑战--易氧化、铜线硬度大等,提出...     

镀钯铜线键合中FAB表面的钯覆盖

铜引线键合由于低廉的成本和优良的材料综合性能而受到越来越多的重视,而镀钯铜线较纯铜线的应用更为广泛。其中,自由空气球(FAB)上钯的覆盖情况是需要进行研究的问题之一。由于烧球工艺为瞬态过程,因此在形成FAB后其表面的钯可能会出现不均匀的分布,后续的塑封环节中低含量的钯区域就会遭受外界的侵蚀,这对焊点的可靠性会有不良的影响。基于此,针对线径20μm镀钯铜线FAB上的钯覆盖区域进行了探究,并采用定制化的化学腐蚀方案来显示FAB上钯膜较厚区域和较薄区域在形貌上的差异。此外还讨论了不同电子火焰熄灭(EFO)工艺参数样品的钯薄弱区形状参数,最后分析了影响FAB表面上钯薄弱区的主要工艺因素,得到了相关工艺参数参考值,对后续工艺的可靠性提升有一定的借鉴意义。     

镀Pd Cu线键合工艺中Pd行为研究

由于Cu线热导率高、电性能好、成本低,将逐渐代替传统Au线应用于IC封装.但Cu线键合也存在Cu材料本身固有特性上的局限:易氧化、硬度高及应变强度等.表面镀Pd Cu线材料的应用则提供了一种防止Cu氧化的解决方案.然而,Cu线表面的Pd层很可能会参与到键合界面形成的行为中,带来新的问题,影响到Cu线键合的强度和可靠性.对镀Pd Cu线键合工艺中Pd的行为进行了系统的研究,使用了SEM,EDS等分析手段对cu线、烧结Cu球(FAB)、键合界面等处Pd的分布状况进行了检测,结果证明Pd的空间分布随着键合工艺的进行发生了很大的变化,同时还对产生Pd分布变化的原因进行了分析和讨论.     

微电子器件封装铜线键合可行性分析

虽然在集成电路封装工艺中金导线键合是主流制程,但是目前采用铜导线替代金导线键合已经在半导体封装领域形成重要研究趋势。文章对微电子封装中铜导线键合可行性进行了分析,主要包括铜导线与金导线的性能比较(包括电学性能、物理参数、机械参数等),铜导线制备和微组织结构分析,铜导线焊合中的工艺研发及铜导线焊合可靠性分析等。当今半导体生产商关注铜导线不仅是因为其价格成本优势,更由于铜导线具有良好的电学和机械特性,同时文中也介绍了铜导线键合工艺存在的诸多问题和挑战,对将来铜导线在集成电路封装中的大规模应用和发展具有一定的参考意义。     

引线键合的低成本解决方案

最近,金价不断上涨突破了35.4美元/g,同时半导体产品特别是存储器类产品的价格却不断下降。目前半导体行业最大的挑战是如何控制并降低成本。为了降低引线键合的原材料成本,近年来金-银合金引线已被开始用来替代金线键合。但是,由于金-银合金引线键合的器件在测试中出现的故障,不能用于在高湿度环境下进行可靠性测试(例如PCT测试)的器件,使其在应用上受到限制。研究了传统Au-Ag合金引线键合的电子器件在PCT测试时所产生的故障机理和钯元素的作用,通过在Au-Ag合金引线中掺入(Pd)钯元素来阻止在高湿度环境下进行可靠性测试时出现的故障。     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame.The gold wire bonding process has been widely used in LED packaging industry currently.However,due to the high cost of gold wire,copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving.In this paper,the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation.This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

IC键合铜线材料的显微力学性能研究

用于IC(集成电路)的键合铜线材料具有低成本、优良的导电和导热性等优点,但其高硬度容易对铝垫和芯片造成损伤,因此对其硬度的测量是一项关键技术。纳米压痕测量技术可以方便、准确地测量铜线材料的显微硬度值和其他力学性能参数。描述了纳米压痕测量技术的原理以及对铜线材料样品进行纳米压痕测量的参数选择,进行了测量试验。结果表明,原始铜线、FAB(金属熔球)、焊点的平均硬度分别为1.46,1.51和1.65GPa,为键合铜线材料的选择和键合工艺参数的优化提供了依据。     

铜丝球键合工艺及可靠性机理

文章针对铜丝键合工艺在高密度及大电流集成电路封装应用中出现的一系列可靠性问题,对该领域目前相关的理论和研究成果进行了综述,介绍了铜丝球键合工艺、键合点组织结构及力学性能、IMC生长情况、可靠性机理及失效模式。针对铜丝球键合工艺中易氧化、硬度高等难点,对特定工艺进行了阐述,同时也从金属间化合物形成机理的角度重点阐述了铜丝球键合点可靠性优于金丝球键合点的原因。并对铜丝球键合及铜丝楔键合工艺前景进行了展望。     

铜引线键合中影响焊球硬度因素的研究

铜丝球焊由于其经济优势和优越的电气性能近来得到了普及,然而,在引线键合工艺中用铜丝取代金丝面临着一些技术上的挑战。多年来,IC芯片焊盘结构已经逐步适应了金丝球焊。铜在本质上比金硬度高,因此以铜线取代金线便引出了有关硬度的问题。研究了用25．4μm铜丝球焊中与键合机参数有关的铜焊球硬度特性。采用电子打火系统不同的电流和打火时间设置,用5％氢气和95％氮气组成的惰性保护气体形成了一个典型的25．4μm大小的铜焊球,研究了维氏硬度的焊球。用实验设计建立了第一和第二键合参数,进行了无空气焊球基本数据调整。通过改变电子打火系统参数。对硬度特性进行了进一步的测试。典型的键合球的大小和厚度的第一键合响应证实铜键合球的生产实力与电子打火系统的电流和打火时间有关．     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

Ultra-fine pitch palladium-coated copper wire bonding: Effect of bonding parameters

Copper (Cu) wire bonding has become a mainstream IC assembly solution due to its significant cost savings over gold wire. However, concerns on corrosion susceptibility and package reliability have driven the industry to develop alternative materials. In recent years, palladium-coated copper (PdCu) wire has become widely used as it is believed to improve reliability. In this paper, we experimented with 0.6 ml PdCu and bare Cu wires. Palladium distribution and grain structure of the PdCu Free Air Ball (FAB) were investigated. It was observed that Electronic Flame Off (EFO) current and the cover gas type have a significant effect on palladium distribution in the FAB. The FAB hardness was measured and correlated to palladium distribution and grain structure. First bond process responses were characterized. The impact of palladium on wire bondability and wire bond intermetallic using a high temperature storage test was studied.