具有64位数据检纠错功能的FPGA模块设计

星载计算机系统中电子器件容易受到空间环境电磁场的辐射和重粒子的冲击,从而导致器件运行出错,特别是存储器中数据容易出现错误,需要具有检纠错功能的电路模块对其进行纠正,以免造成严重的后果.基于汉明码的纠错原理,根据对64位数据进行检纠错处理的需要,设计一个利用8位校验码,以实现该功能的算法逻辑,并通过FPGA实现.经过仿真验证,该模块具备检测2位错误,纠正1位错误的功能,而且也能较好地满足实时性的要求,具有一定的实际应用意义.     

基于龙芯LA132软核处理器的宇航级SoPC设计

针对现有星载计算机主控系统灵活性差和在空间辐射环境中存在单粒子翻转等问题,设计了一种灵活性强、可靠性高、自主可控的宇航级片上可编程系统(System-on-Programmable-Chip, SoPC)。该系统将龙芯LA132软核处理器应用于航天领域,降低了星载计算机主控系统的体积。为系统存储单元设计实现了一种基于矩阵算法的RS(8,4)码,可在无延迟的情况下实现错误检测与纠正功能,增强了系统的可靠性。测试结果表明,该SoPC系统在Xilinx KCU105硬件平台上可实现单周期内对两个错误符号的检测与纠正,满足宇航级安全性与可靠性的需求,为星载计算机主控系统的小型化提供了一种新的解决方案。     

一种改进的对抗软错误电路结构设计

给出了一种改进的基于时钟沿的自我检测和纠正的电路结构,以纠正由单粒子翻转（SEU）引起的数据错误。简单概述了已有的检测和纠正SEU的电路结构,并在该电路的基础上提出了改进的电路结构,以实现对触发器以及SRAM等存储器的实时监控,并可以及时纠正其由于SEU引起的数据错误。采用内建命令进行错误注入模拟单粒子翻转对电路的影响。改进的电路与原来的电路相比,以微小的面积和较少的资源换取更高的纠错率。     

一种抗SEU存储器电路的FPGA设计

为了改善星载存储器的抗SEU性能,增加星载存储器在空间使用的灵活性,文中基于ACTEL公司的ProAsic系列A3P400FPGA并采用扩展汉明码和TMR两种检错纠错方法相结合的方式,同时使用可变内存配置方案,设计了一种新型的抗SEU存储器电路。与传统的EDAC芯片相比,本设计不仅可以对出错数据进行修正而且还可以实时的进行回写。     

基于FPGA和NAND Flash的存储器ECC设计与实现

针对以NAND Flash为存储介质的高速大容量固态存储器,在存储功能实现的过程中可能出现的错“位”现象,在存储器的核心控制芯片,即Xilinx公司Virtex-4系列FPGA XC4VLX80中,设计和实现了用于对存储数据进行纠错的ECC算法模块。在数据存入和读出过程中,分别对其进行ECC编码,通过对两次生成的校验码比较,对发生错误的数据位进行定位和纠正,纠错能力为1 bit/4 kB。ECC算法具有纠错能力强、占用资源少、运行速度快等优点。该设计已应用于某星载存储系统中,为存储系统的可靠性提供了保证。     

一种含BCH编解码器的SLC／MLC NAND FLASH控制器的VLSI设计

为了满足存储器市场对低单比特成本和高存储密度的需求,在一款基于ARM926EJ的片上处理器芯片中,集成了一个可支持SLC/MLC NAND FLASH的控制器.为了纠正FLASH存储器芯片中的随机错误,采用了可纠4比特错误的BCH纠错码,该纠错码非常适应NAND类型存储器的随机错误特点.该控制器可支持多种类型的NAND FLASH.另外,对一种基于伯利坎普-梅西算法的高效BCH编解码器VLSI结构进行了研究,采用一种简化伯利坎普-梅西算法实现的低复杂度的关键方程解算机消除其速度瓶颈.芯片采用SMIC 0.13 μm CMOS工艺.测试结果证明,设计电路完全符合系统规范,性能表现优良.     

基于EDA的纠错编码及数据交织ASIC的设计

为了纠正数字通信中的随机错误和突发错误，提出了一种卷积编码和数据交织技术相结合的纠错编码方案，介绍了基于EDA技术的卷积纠错电路和数据交织器的设计方法，最终实现了利用MAX＋plusⅡ对纠错系统的设计集成，形成了卷积编码和数据交织ASIC。仿真表明，该方案工作稳定，纠错性能与单独的卷积纠错法相比有很大改善。     

一种高可靠大容量星载存储器的设计与研究

凭借着存储密度大和存储速率高的特点,基于NANDFlash的大容量存储器在星载存储领域得到了广泛的应用,由于NAND Flash本身存在缺陷,基于NAND Flash的大容量存储器在恶劣环境下的可靠性难以保证.提出了通过FPGA设计SRAM对关键数据三模冗余读取和缓冲、NAND Flash阵列热备份和数据的回放校验以及合理的坏块管理等措施,实现了高可靠性的大容量存储器.实验说明该系统不会因为外在偶然因素而造成数据的不完整,而且整个存储系统的成本开销相对于目前的星载存储器也非常低.     

基于一种交织码的多位翻转容错技术研究

随着技术的发展和核心电压的降低,存储器更易受瞬时错误（软错误）影响,成为影响航天器件可靠性的主要原因。错误检测与纠正（EDAC）码（也称错误纠正码）常用来对SRAM型存储器中的瞬时错误进行纠正,由单个高能粒子引起的多位翻转错误（SEMU）是普通纠一检二（SEC-DED）编码所无法处理的。提出了一种交织度为2的(26,16)交织码,该码由两个能纠正一位随机错误、二位突发错误的(13,8)系统码组成,(26,16)交织码能够纠正单个码字中小于二位的随机错误和小于四位突发错误（DEC-QAEC）。通过理论分析和硬件平台实验表明,该交织码在存储资源占用率、实时性相当情况下可靠性优于同等长度的SEC DED码,能有效提高SRAM型存储器抗多位翻转错误的能力。      

基于CPLD与CCD的光谱测量数据采集系统设计

介绍了CCD的工作原理和相关双采样的原理,设计了一种基于CPLD与CCD的数据采集系统。利用Verilog语言编程产生CCD和AD9844的驱动时序,AD9844对CCD输出信号进行相关双采样并进行A/D转换,采集到的数据存储至外部存储器。最后,用单片机实现与计算机的串口通信,完成将存储器中的数据传输至计算机。该系统完成了光谱测量数据的快速采集、存储及数据处理,并进行了实验验证。结果表明,该系统具有电路结构简单、成本低、程序修改方便等特点,在光谱分析领域具有一定的应用价值。     

RS（16,12）缩短码编译码原理及性能分析

在各类数字通信系统以及计算机存储和运算系统经常利用差错控制编码降低误码率,提高通信质量,满足对数据传输通道可靠性的要求。RS码是一种性能优良的前向纠错码,具有同时纠正随机错误和突发错误的能力,它的构造特点决定了其非常适合于纠正突发性错误。文中在阐述RS系统码编译码原理的基础上,提出了RS（16,12）缩短码的编译码方法,利用MATLAB对R S（16,12）缩短码在高斯信道和瑞利信道条件下的纠错能力进行仿真,并分析其纠错性能。     

平面近场测量中取样位置误差修正方法的研究

本文提出一种修正近场天线测量中探头集团误差的方法－非线性迭代法。探头的集团误差为可知值,同激光定位系统获得。运用泰载级数展开,可将天线理想波谱表示为误差算子和近场测量数据的形式。通过计算机械模拟,得到迭代修正后精确的近场值。本文在理想值、有误差的值和修正误差后的值之间作了些比较,相应的模拟数据有助于证实此结合。     

Construction techniques for systematic SEC-DED codes with singlebyte error detection and partial correction capability for computermemory systems

Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per byte     

P 波段雷达成像电离层效应的地面观测与校正

对于高分辨率星载P 波段SAR 系统,电离层效应对P 波段SAR 会带来一系列较为严重的误差,这些误差与电波频率和电离层积分电子总量(TEC)值关系密切,并使得图像质量下降。为了获得高质量的图像,必须对电离层误差进行校正。该文基于电离层导致的匹配滤波失配的数学模型,指出获得准确的电离层TEC 是校正的关键,提出了一种高精度的基于SAR 回波相位反演电离层TEC 的测量方法,并利用地基P 波段雷达对空间目标进行穿透电离层步进频ISAR 观测验证,实测数据处理结果表明,该方法有效提高了电离层TEC 测量精度,改善了ISAR成像质量,可适于低频段星载SAR 系统的电离层效应测量与校正应用。      

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.     

Offline correction of microwave-network-analyser reflection-coefficient errors

This program has been developed to correct certain errors arising in the use of microwave-network-analyser systems. In using a network analyser to measure the reflection coefficient, errors arise from imperfections in directional couplers, source and other mismatches and crosstalk and inaccurate tracking between test and reference channels. This program facilitates calibration of the system and corrects the measurement data obtained. The use of error correction can also extend the useful frequency range of the analyser. In addition, the program can modify data for various reference planes and has facilities for graphical output on a Smith-chart display. The program was designed to run on an ICL 4100 series computer with incremental plotter, magnetic tape handlers and paper-tape station, in addition to card reader and line-printer.     

基于计算机视觉图像精密测量的关键技术研究

虽然计算机视觉系统已经成功地应用于某些检测任务,但由于尺寸畸变和误差的存在,它们一般不被认为是精确的测量工具。本文介绍了精密测量中这些误差的修正方法。第一步是利用神经网络建立图像坐标系的标定模型。然后利用标准件构造学习阶段的神经网络模型,对初始测量的尺寸误差进行建模。最后利用这些模型对测量任务中的测量误差进行校正。     

SDRAM在大视场TDICCD空间相机中的应用

该文针对大视场空间相机中需要缓存的图像数据量大的问题,对高速大容量存储器SDRAM控制技术进行了研究。首先,说明了大视场空间相机中图像数据缓存的需要,根据CCD图像数据和图像缓存工作特点,提出了基于行使能和刷新操作驱动和基于仲裁策略的SDRAM控制器。然后,为了提高图像数据缓存可靠性,针对缓存小数据量场合,提出了(6,8)纠错算法,针对缓存大数据场合提出了RS(143,127)和RS(142,126)码纠错算法。最后,在XX-X空间多光谱相机样机的成像系统上进行了试验验证。实验结果表明:两种控制器工作频率能够达到131 MHz,正常工作时,行使能驱动控制器存取速度达到127.08 MBps,仲裁策略控制器存取速度达到139.788 MBps,两种纠错算法在507 B/row内可以纠正32 b错误。基本满足空间相机中的稳定可靠、高效率的缓存图像数据要求。     

Adaptive alignment packaging for 2-D arrays of free-spaceoptical-interconnected optoelectronic systems

An adaptive alignment scheme for packaging two-dimensional (2D) arrays of optoelectronic systems interconnected by free-space optics is presented. A method of using three quadrant detectors to detect alignment errors in six degrees of freedom is described. However, the complexity of this system increases due to the interactions among the detected error signals. A novel control algorithm is presented to eliminate the interaction and simplify the design of the closed-loop feedback control. A computer simulation compares different algorithms and shows the effectiveness of the proposed algorithm. An experimental closed-loop feedback system demonstrated the principle of the error detection and correction of the proposed system with initial errors in multiple degrees of freedom     

Software-implemented EDAC protection against SEUs

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment