叠层CSP芯片封装热应力分析与优化

对四层叠层CSP（SCSP）芯片封装器件,采用正交试验设计与有限元分析相结合的方法研究了芯片和粘结剂——8个封装组件的厚度变化在热循环测试中对芯片上最大热应力的影响．利用极差分析找出主要影响因子并对封装结构进行优化。根据有限元模拟所得结果．确定了一组优选封装结构,其Von Mises应力值明显比其它组低,提高封装器件的可靠性。     

DFN封装翘曲和应力分析与优化

回流焊过程中,双边扁平无引脚(DFN)封装会因为巨大的温度变化产生翘曲和应力,影响超高频射频识别(RFID)芯片的性能和可靠性.选取DFN3封装为例从理论方面分析结构和材料参数对封装翘曲和应力的影响,发现减小环氧塑封料(EMC)热膨胀系数(CTE)、增大其杨氏模量均能减小封装翘曲;通过有限元仿真分析得出的结论与理论分析相一致.为了减小封装翘曲和应力,选定具有更小CTE的9240HF10AK-B3(Type R)作为新型EMC.通过有限元仿真结果对比发现,在25℃时,采用新型EMC的封装翘曲增大了 16.8％,应力减小了 4.1％;260℃时,其封装翘曲减小了 45.7％,应力减小了 9.2％.同时,新型EMC的RFID芯片标签回波损耗较之前优化了 6.59％.     

多芯片叠层封装中的芯片应力分析及结构优化

针对典型的四层芯片叠层封装产品,采用正交试验设计与有限元分析相结合的方法研究了芯片、粘合剂、顶层芯片钝化层和密封剂等十个封装组件的厚度变化对芯片上最大热应力的影响,并利用找到的主要影响因子对封装结构进行优化.结果表明,该封装产品可以在更低的封装高度下实现,并具有更低的芯片热应力水平及更小的封装体翘曲,这有助于提高多芯片叠层封装产品的可靠性.     

叠层封装技术

首先介绍叠层封装技术的发展现状及最新发展趋势,然后采用最传统的两层叠层封装结构进行分析,包括描述两层叠层封装的基本结构和细化两层叠层封装技术的SMT组装工艺流程。最后重点介绍了目前国际上存在并投入使用的六类主要的叠层封装方式范例,同时进一步分析了叠层封装中出现的翘曲现象以及温度对翘曲现象的影响。分析结果表明:由于材料属性不同会引起正负两种翘曲现象;从室温升高到150℃左右的时候易发生正变形的翘曲现象,在150℃升高至260℃的回流焊温度过程中多发生负变形的翘曲现象。     

叠层QFN器件界面层裂失效研究

为了探究造成微电子封装器件界面层裂的根源,选取了叠层QFN器件进行建模仿真,模拟了其在热加载条件下的器件应力分布情况。通过粘结强度实验,测出加载力与位移的关系,其中力的峰值为2.52N,裂纹开口位移为0.29mm,计算得到的界面断裂能为10.5N/m。采用内聚力模型(CZM)与J积分这两种数值预测方法,对芯片粘结剂与铜引脚层界面层裂失效作了研究,找到裂纹萌生的关键点;两者对裂纹扩展趋势的结论一致,在预测裂纹产生方面,CZM法比J积分法更方便。     

LCCC封装器件热疲劳失效分析及结构优化研究

针对LCCC封装器件在温度循环载荷下焊点开裂的问题,首先分析其失效现象和机理,并建立有限元模型,进行失效应力仿真模拟。为降低焊点由封装材料CTE不匹配引起的热应力,提出了两种印制板应力释放方案,并分析研究单孔方案中不同孔径和阵列孔方案中不同孔数量对热疲劳寿命的影响。之后,为降低对PCB布局密度的影响,提出一种新型的叠层焊柱应力缓冲方案,进行了不同叠层板厚度和焊柱间距的敏感度分析。结果表明,更大的开孔面积、更小的叠层板厚度、更密的焊柱可有效降低焊点应力,提高焊点热疲劳寿命,使得LCCC封装器件焊点热疲劳可靠性得到有效提高。     

QFN封装分层失效与湿-热仿真分析

采用湿度敏感度评价试验及湿-热仿真方法,分析了温湿度对于QFN封装分层失效的影响.通过C-SAM和SEM等观察发现,QFN存在多种分层形式,分层大多发生在封装内部材料的界面上,包括封装塑封材料和芯片之间的界面、塑封材料和框架之间的界面等.此外,在封装断面研磨的SEM图像上发现芯片粘结剂内部有空洞出现.利用有限元数值模拟的方法,对QFN封装的内部湿气扩散、回流过程中的热应力分布等进行了模拟,分析QFN分层失效的形成原因.结果表明,由于塑封器件材料、芯片、框架间CTE失配,器件在高温状态湿气扩散形成高气压条件下易产生分层.最后提出了改善QFN分层失效的措施.     

大尺寸LTCC焊接组件热变形特性的仿真研究

为了研究不同封装条件对低温共烧陶瓷(LTCC)基板封装焊接后残余热应力的影响,该文针对不同温变载荷下LTCC基板的热应力变形进行了仿真计算和实验测试,结果显示仿真计算与实验测试结果具有较好的一致性,验证了数值仿真用于LTCC基板封装焊接后残余热应力仿真的可行性。在此基础上对零膨胀合金底板和硅铝合金封装条件下3种典型工作温度对应的LTCC基板的热应力进行了仿真计算。结果表明,封装焊接后LTCC基板两侧边缘应力集中,中间残余应力小,呈翘曲状态,采用硅铝合金封装焊接的热应力小于零膨胀合金封装。     

基于蒙特卡罗法的QFN器件可靠性灵敏度分析

采用有限元软件,在热循环加载条件下,对四角扁平无引脚封装(QFN,Quad Flat No-lead Package)器件进行了热疲劳可靠性分析。选取PCB焊盘长度等几个因素作为灵敏度分析的输入变量,热疲劳寿命作为输出变量。结果表明:影响QFN器件热疲劳寿命的主要因素依次是焊盘长度、焊盘宽度和焊盘弹性模量等,其灵敏度值分别为:–6.4848×10–1,6.0606×10–1和6.0000×10–1等。提出了提高QFN器件可靠性的方法。     

湿热环境下吸潮对QFN器件可靠性的影响研究

由吸潮引起的微电子塑封器件失效已经越来越多地引起人们的关注.选用QFN器件作为研究对象,首先进行QFN器件在高温高湿环境下吸潮17 h、50 h、96 h试验;然后利用有限元软件分析和模拟潮湿在QFN器件中的扩散行为,并建立湿气预处理阶段应力计算模型;最后,通过试验与仿真相结合,分析潮湿对封装可靠性的影响.研究表明:微电子塑封器件的潮湿扩散速度与位置有着重要的关系;在高温高湿环境下,微电子器件吸潮产生的湿热应力在模塑封装材料(EMC)、硅芯片(DIE)和芯下材料(DA)的交界处最大;QFN器件在高温高湿环境下吸潮产生的裂纹主要出现在硅芯片与DA材料交界面的边界.     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

Characterization of the Effect of Shape Memory Alloy on Solder Joint Strength Through Modeling and Testing

Currently some of the most common problems that surface mount technology encounters are warpage, delamination, and inelastic strain concentration accumulated in the solder joint during thermal cycling because of mismatch of thermal expansion coefficient between the package and chip side. Material as well as package structure are the critical issues with respect to these problems. The objective of this research is to investigate how shape memory alloy (SMA) applied in the under bump metallization (UBM) can affect solder joint reliability under thermal mechanical stress. Joint strength tests revealed the better strength of solder joints with SMA UBM after accelerated thermal cycling test. Finite element modeling as well as multilayer stress calculations revealed less strain accumulated in the solder and more stress concentrated in Si in the solder joint with SMA UBM. A mechanism by which the SMA accommodates most of the stress and strain caused by the mismatch of the thermal expansion coefficients was proposed to explain the reinforcement of the solder joint by the SMA UBM.     

基于析因实验设计的QFN热可靠性分析

在微电子封装器件的生产或使用过程中,由于封装材料热膨胀系数不匹配,不同材料的交界处会产生热应力．热应力是导致微电子封装器件失效的主要原因之一。采用MSC．Marc有限元软件．分析了QFN器件在回流焊过程中的热应力、翘曲变形、主应力及剪应力,并由析因实验设计得到影响热应力的关键因素。研究表明：在回流焊过程中,QFN器件的最大热应力出现在芯片与粘结剂接触面的边角处：主应力和剪切应力的最大值也出现在芯片与粘结剂连接的角点处．其值分别为21．42MPa和-28．47MPa：由析N实验设计可知粘结剂厚度对QFN热应力的影响最大。     

基于析因实验设计的QFN热可靠性分析

在微电子封装器件的生产或使用过程中,由于封装材料热膨胀系数不匹配,不同材料的交界处会产生热应力,热应力是导致微电子封装器件失效的主要原因之一。文章采用MSC．Marc有限元软件,分析了QFN器件在回流焊过程中的热应力、翘曲变形、主应力及剪应力,并由析因实验设计得到影响热应力的关键因素。研究表明：在回流焊过程中,QFN器件的最大热应力出现在芯片与粘结剂接触面的边角处;主应力和剪切应力的最大值也出现在芯片与粘结剂连接的角点处,其值分别为21．42MPa和-28．47MPa;由析因实验设计可知粘结剂厚度对QFN热应力的影响最大。     

Warpage evolution of overmolded ball grid array package during post-mold curing thermal process

Two of the main driving forces for warpage deformation and residual stress in electronic packages are the thermal expansion mismatch between dissimilar package constituents and the crosslinking reaction of polymers during packaging thermal processes. For the purpose of quantitatively characterizing these two driving forces and assessing the process effect on warpage deformation, experimental and numerical analyses were applied to study the warpage evolution of overmolded ball grid array (BGA) package under post-mold curing (PMC) thermal histories. From in situ shadow Moiré warpage analyses on bimaterial and package specimens, it was observed that, during the isothermal curing condition, a significant increase in specimen warpage occurred as a result of molding compound shrinkage. A numerical modeling procedure that incorporates the models for the thermochemical cure kinetics, the curing- and chemical aging-induced shrinkage strains, and the cure-dependent viscoelastic relaxation modulus for the molding compound was then applied to simulate and compare to the experimentally obtained warpage evolutions. It can be seen from the analysis results that the evolution of package warpage over multiple thermal histories can be superpositioned by the thermal expansion mismatch-driven warpage change during non-isothermal stages and the chemical shrinkage-induced warpage evolution during isothermal aging at temperatures above the material glass transition point.     

脉冲激光线源激发金属圆管中冯．密赛斯应力的研究

在得到的温茺场分布的基础上,用有限元结构分析法数值模拟了金属圆管中脉冲激光线源产生的主应力场情况,得到了铝管中不同时刻的冯．密赛斯应力场,给出了不同时刻冯,密赛斯应力随周向和法向的分布以及等值图分布情况。数值结果表明：在激光加载中心点处冯．密赛斯应力值最大,冯．密赛斯应力随周向和法向的变化情况和温度场的变化类似。