A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

A 2Gb/s throughput GaAs digital time switch LSI using LSCFL

A GaAs four-channel digital time switch LSI with a 2.0-Gb/s throughput is developed. This switch consists of 4-bit shift registers, data latches, a counter, a control unit, and I/O buffer gates. The LSI includes 1176 devices (FET's, diodes, and resistors) and its equivalent gate number is 231 gates. Low Power Source Coupled FET Logic (LSCFL) operating in a true/complementary mode is used to ensure high-speed and low-power performance. MESFET's with 0.55-µm gate length are fabricated by the buried p-layer SAINT process, which satisfactorily suppresses short channel effects. Dislocation-free wafers are also used to provide high chip yields of 75 percent. The propagation delay time of the LSCFL basic circuit is 48 ps/gate with 1.4-mW/equivalent gate. The total power dissipation including input and output buffers is 0.64 W. The LSI speed performance is evaluated by measuring toggle frequency of the 1/4 frequency divider. The divider operates typically at 5.1 GHz, maximum 7.5 GHz. The newly developed high-speed digital time switch LSI makes possible time division switching services in TV and high-definition TV transmission systems.     

A 1.5 Gbit/s GaAs four-channel selector LSI with monolithicallyintegrated newly structured GaAs ohmic contact MSM photodetector andlaser driver

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabrication yields can be routinely achieved. Performances which can be achieved with this approach have been tested by means of a single-clocked frequency divider circuit fabricated with MESFETs of 1 /spl mu/m/spl times/20 /spl mu/m gate geometry.     

An InGaAs/GaAs MQW optical switch based on field-induced waveguides

A novel optical waveguide switch containing InGaAs/GaAs multiple-quantum wells (MQW) is proposed. In this structure, a large field-induced refractive index increase (0.1%) due to the quantum-confined Stark effect (QCSE) is utilized to generate electrically controllable waveguides. Switching operation of a first fabricated device has been investigated at wavelengths of about 1 μm. A crosstalk ratio of -18.8 dB and an extinction ratio of 20.9 dB was achieved at a reverse voltage of -7 V. Within an operational wavelength region of 9 nm, crosstalk was found to be less than -13 dB for both switching conditions. Further, the proposed switch structure seems to be well suited for monolithic integration with laser diodes and exhibits the potential for high-speed operation     

A gigabit-rate five-highway GaAs OE-LSI chipset for high-speedoptical interconnections between modules or VLSIs

A gigabit-rate five highway interface GaAs optoelectronic LSI chipset has been fabricated for the 0.85 μm wavelength range optical interconnections between modules or VLSIs. The optical sender consists of a high-speed laser driver array LSI having 2 Gb/s maximum operation speed and a tiny laser array. The optical receiver in a GsAs high-speed optical receiver array LSI with a monolithically integrated metal-semiconductor-metal (MSM) photodetector, a high-speed preamplifier, and a decision circuit that has a maximum operation speed of 1.8 Gb/s. The receiver LSI is provided with a new bit-synchronizing circuit and an automatic threshold determination circuit     

High-Speed Digital Switching Technology Using Space-Division-Switch LSI's

NTT is planning a high-speed broad-band switching network that offers high-speed digital and 4 MHz video services. This paper discusses the hardware design of the high-speed space-division digital switching network and requirements for a switch LSI. In addition, the design and measured performance of a 32 × 32 CMOS space-division-switch LSI are described. In this network, video signals are converted into 32 Mbit/s digital signals by band-compression technology. In order to switch such digital signals, space-division switches are more advantageous than time-division switches. This is because time-division switches cannot multiplex many channels at that bit rate. Furthermore, the use of the space-division-switch LSI is the most effective way to miniaturize the switching system.     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems     

1 Gbit/s, 32*32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections.<>     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

1-V power supply high-speed digital circuit technology withmultithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-μm CMOS process     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

GaAs 1 kbit static RAM with self-aligned FET technology

A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns address access time with 369 mW power consumption. The minimum write-enable pulsewidth is less than 2 ns. The maximum number of good bits is 1001 bits/1024 bits. The problems of mass production of GaAs LSI are discussed.