自顶向下制备硅纳米线环栅MOSFET新工艺

准弹道输运特征的环栅纳米线MOSFET由于具备很强的栅控能力和抑制短沟道效应的能力,被认为是未来22nm技术节点以下半导体发展路线最有希望的候选者之一。采用传统CMOS工艺在SOI和体硅衬底上制备环栅纳米线MOSFET,解决了许多关键的技术难点,获得了许多突破性进展。文章综述了目前各种新颖的自顶向下制备方法和各种工艺的优缺点,以及优化的方向。     

Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs)

The characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with a radius of 5 nm have been measured in temperatures T ranging from 4 to 300 K. The dependence of the off-current suggests that thermal generation in the channel is the main leakage mechanism. The dependence of the subthreshold swing exhibits no body effects but shows degradations due to slight differences in the threshold voltages and in the body effect constants of the twin nanowires. The T dependence of the peak normalized transconductance g_m /V_DS gives a clue of 1-D phonon scattering and suggests that surface roughness scattering at the nanowire wall is dominant at low values.     

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.      

光电化学腐蚀法制备高长径比硅微通道

在高长径比硅微通道光电化学腐蚀中,需要根据通道尺寸要求实时修正腐蚀电流.研究了物质输运、暗电流对腐蚀电流控制的影响,并提出了腐蚀电流的控制曲线.根据电解液扩散方程和边界条件,推导出通道尖端处HF质量分数与通道长度的关系.根据腐蚀后的暗扫描I-V曲线计算出暗电流密度.与腐蚀电流密度相比,阴离子表面活性剂的暗电流可忽略不计,进而获得了腐蚀电流修正曲线.根据腐蚀电流修正曲线,通过控制光照强度制备出高长径比(大于60)的等径硅微通道阵列.对修正的腐蚀电流进行调整,制备出通道尺寸空间周期性变化的硅微通道结构.研究结果可为高长径比硅微通道的制备提供技术方法.     

基于ICP的硅高深宽比沟槽刻蚀技术

介绍了电感耦合等离子体(ICP)刻蚀技术的基本概念。结合英国STS公司的STS multiplex ICP system刻蚀机,介绍了刻蚀机原理及刻蚀过程。对硅深槽刻蚀技术进行了分析,对其中Footing效应、Lag效应和侧壁光滑问题提出了优化方案,最后在实验的基础上得出了能够刻蚀出高质量硅深沟槽的刻蚀参数。     

Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations.     

深槽LIP太阳能电池栅线电极技术

介绍了深槽LIP太阳能电池栅线电极的制造方法,对LIP工艺及装置进行了详细的说明。通过试验表明,用新工艺制造的太阳能电池片的转换效率可达19.4%。讨论了与传统工艺相比较,深槽LIP太阳能电池片在光学和电学性能上的提升机理。     

Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs including interface traps

This paper presents a systematic investigation of flicker noise in Gate-all-around Silicon Nanowire MOSFET. The 1/f noise is simulated in the presence and absence of interface traps. Moreover the device is simulated under various distributions (Exponential, Gaussian, Uniform) of noise source. Nonuniformity in the interface of the oxide/semiconductor region as gave rise to increase the threshold voltage, there by increasing the leakage current. The effect of interface traps on different distribution has been explored in detail. The noise spectral density variations for various traps shows significant increase in flicker noise up to a magnitude of under 6 “dB” for weak signals. The simulated results matches with the calibrated experimental data.     

硅基高长径比深孔阵列的制作研究

高长径比深孔阵列是微通道板、高分辨率X射线探测器、X射线二维光栅等器件的基本结构。基于制作大面积高长径比的深孔阵列目前仍是微纳制作技术面临的重大挑战。介绍了几种硅基微孔阵列的制作方法并分析了这几种方法的优劣。提出了用光助电化学刻蚀方法在硅基上制作大面积高长径比的深孔阵列,并从实验上研究了溶液浓度、温度、硅片掺杂浓度、光照条件、电流和电压等刻蚀过程参数对深孔微结构形貌的影响。最后给出了最佳刻蚀过程的实验参数,在整个5英寸(1英寸=2.54 cm)n型硅圆片上得到了长径比在40以上、有效圆面直径达110 mm的深孔阵列。     

Microwave Characterization and Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in Silicon Substrates

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-$mu$m-in diameter on 400-$mu$m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-$mu$m via, the inductance and resistance are measured to be 254 pH and 0.1$Omega$, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.     

高厚径比盲孔电镀

盲孔能够大大的增加板的密度,从而减小板面积。介绍了有关高厚径比盲孔电镀的有关工艺,从激光钻孔、金属化孔和电镀几个方面对孔径4mil以上的盲孔电镀进行了研究。     

高厚径比贯通孔的无添加剂电镀

在多层印制线路板中,为了在贯通孔中生产出均匀厚度的铜镀覆层,加上这些多层PWB持续地发展更厚的板和更小的贯通孔,以满足表面安装技术(SMT)的发展要求,其结果导致孔内镀层厚度均匀性电镀的困难.一系列改进的技术,如射流喷射、化学蒸汽沉积(CVD,Chemical Vapor Deposition)、全加成化学镀和调整(酸性镀铜)等来满足高厚径比多层板制造者的要求.但是这些技术由于高投资,与环境不友善、长的电镀时间、不均匀的镀层厚度,或者要取决于专用(利)的添加剂等.同时,这些技术随着高厚径比的增加而变得越来越无效.但是用于高厚径比的贯通孔和导通孔的周期反向电流(PRC,PeriodicReverse Current)电沉积可获得明显的镀层均匀性和提高生产率,而且有利于保护环境.我们基于PRC工艺而开发出一种无添加剂的高厚径比电镀铜体系.这种工艺已制备出PTH的样品,其板表面/孔内的镀铜厚度接近于1.同时,所镀得铜箔用于机械特性评价已表明抗拉强度和延展性类似于常规DC有添加剂镀液所制得的铜箔的特性.最后,我们采用PRC并在两倍于常规电流密度的50ASF(约5.4A/dm2)下制得高质量电积铜层.初步的结论表明,PRC电镀可在较高电镀生产率而不用有机添加剂下制得精确的镀层控制特性.通过连续努力开发形成一个Database/algorithm以得到所期望的最佳电镀波形特性.这个Database/algorithm将集成到无添加剂的高厚径比电镀系统中.     

深孔镀锡抗蚀不良解决方案

随着背板的出现,板件厚度越来越高,同时板件的布线密度也越来越大,迫切需要采用精细线路和小孔来应对这种发展趋势。在这种情况下,高厚径比板件将逐渐成为PCB发展的主流。但这将对加工制程提出巨大的挑战,特别是镀锡抗蚀层的退膜蚀刻流程。文章主要针对高AR值（≥8∶1）板件图形电镀制作过程中出现的抗蚀不良孔无铜进行分析和研究,达到提升生产线加工能力和板件品质的目的。     

Comparisons of Performance Potentials of Silicon Nanowire and Graphene Nanoribbon MOSFETs Considering First-Principles Bandstructure Effects

In this paper, we investigate the performance potentials of silicon nanowire (SNW) and semiconducting graphene nanoribbon (GNR) MOSFETs by using first-principles bandstructures and ballistic current estimation based on the “top-of-the-barrier” model. As a result, we found that SNW-MOSFETs display a strong orientation dependence via the atomistic bandstructure effects, and [110]-oriented SNW-MOSFETs provide smaller intrinsic device delays than Si ultrathin-body MOSFETs when the wire size is scaled smaller than 3 nm. Furthermore, GNR-MOSFETs are found to exhibit promising device performance if the ribbon width is designed to be larger than a few nanometers and a finite band gap can be established.      

High Aspect Ratio Vertical Cantilever RF-MEMS Variable Capacitor

An electrostatically actuated, microwave microelectromechanical system variable capacitor fabricated using deep X-ray lithography is presented. A single exposure has been used to produce the novel high aspect ratio microstructure, which includes a thin, vertically oriented, movable nickel cantilever beam and a 40:1 vertical aspect ratio capacitance gap. The 0.8-pF capacitor operates in the 1-5GHz region and has Q-factors of 36 at 4GHz and 133 at 2 GHz. The variable capacitance ratio is 1.24:1 over a 20-V tuning range at 4GHz     

Lateral Buckling of High Aspect Ratio Janus Nanowalls

In recent years, the fabrication of Janus materials and their potential applications has been of much interest in Materials Science. Here, we report the fabrication of an entirely novel structure–Janus nanowalls and the phenomenon of lateral buckling in them. Polymeric nanowalls were prepared with the replica molding technique and metal films, of comparable thicknesses, were then deposited on one side of the polymer nanowalls by vacuum process. During the metal deposition, the nanowalls themselves buckle laterally; this buckling is induced by the compressive residual stress in the metal film and geometric confining constraints. The feature of wrinkle patterns resulting from the lateral buckling was theoretically investigated using the scaling analysis. Theoretical results are in good agreement with the experimental observations.     

Mode Converters for Coupling to High Aspect Ratio Silicon-on-Insulator Channel Waveguides

The design, simulation, and experimental performance of mode converters for coupling from single-mode silicon-on-insulator ridge waveguides to high aspect ratio channel waveguides are described. The converters consist of a two-level adiabatic taper structure. The final channel waveguide is 1.5 mum high by 0.8 mum wide. Simulations predict that for total coupler lengths longer than 20 mum, the coupling loss from the fundamental ridge mode to the slit mode is better than -0.2 dB. The couplers and waveguides were fabricated using a two-step self-aligned process. The measured coupling loss for fabricated mode converters is -0.4 dB     

Biomechanical Cell Regulation by High Aspect Ratio Nanoimprinted Pillars

High aspect ratio pillared topographies provide a large number of mechanical cues that cells can sense and react to. High aspect ratio pillars have been employed effectively to promote stem cell differentiation and to probe cellular tractions. Yet, the full potential of these topographies for mechanobiology remains insufficiently characterized. Here, the response of progenitor neural stem cells to dense high aspect ratio polymer pillars in the nano‐ and microscale is investigated. Thermal nanoimprinting is utilized to fabricate with high precision well‐defined pillars with high density and aspect ratio. Studies on cell viability, morphology, cell spreading, and migration are performed comparatively to a control flat substrate. The traction forces exerted by the cells on the pillar structures are probed quantitatively by a combined focused ion beam scanning electron microscopy (FIB‐SEM) technique. The cell responses observed are distinctive for each dimension, following the trend that an increase in aspect ratio and feature size from nano‐ to micronscale results in more confined cell morphology with large cytoplasmic penetrations and nuclear deformation. Accordingly, cells seeded on the micrometer scale topography show reduced mobility, a persistent quasi‐directional migration, high traction forces, and a lower rate of proliferation. Cells on the nanotopography show higher rate of proliferation, a large cell spread, high mobility with random migration altogether with lower traction forces.     

充填高密度高厚径比导通孔和大量生产装置

概述了来自PCB制造厂的微导通孔填充材料要求和机器加工能力的研究,适宜于高密度高厚径比导通孔的大量生产。     

高厚径比多层板的电镀控制

本文综述了高厚径比多层板特别是厚径比达到3以上的多层板,在制造过程中电镀处理的难点并提出解决方法.