A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm² chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port     

一种基于OFDM的新型低功耗RF收发器设计

为实现低功耗信号传输,提出一种基于OFDM的IEEE 802.15.4g低功耗无线电频率（RF）收发器。该新型RF收发器电路由Tx BBA（基带模拟）、片上RF开关前端、Rx BBA及锁相环（PLL）构成,采用0.18?m CMOS技术制作,满足了IEEE 802.15.4g OFDM系统低功耗信号传输的需要。实际测试结果显示,相比传统的RF收发器,提出的RF收发器具有较低的功耗和良好的灵敏度,当电源电压为1.8 V时,Tx模式下会消耗14.7mA,Rx模式下会消耗15.7mA。     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

This paper presents a fully integrated 0.18-/spl mu/m CMOS Bluetooth transceiver. The chip consumes 33 mA in receive mode and 25 mA in transmit mode from a 3-V system supply. The receiver uses a low-IF (3-MHz) architecture, and the transmitter uses a direct modulation with ROM-based Gaussian low-pass filter and I/Q direct digital frequency synthesizer for high level of integration and low power consumption. A new frequency shift keying demodulator based on a delay-locked loop with a digital frequency offset canceller is proposed. The demodulator operates without harmonic distortion, handles up to /spl plusmn/160-kHz frequency offset, and consumes only 2 mA from a 1.8-V supply. The receiver dynamic range is from -78 dBm to -16 dBm at 0.1% bit-error rate, and the transmitter delivers a maximum of 0 dBm with 20-dB digital power control capability.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A switch‐controlled multimode narrowband receiver RF front‐end

This work illustrates a flexible and convenient method to build a multimode narrowband receiver RF front‐end by means of controlled switches, switched capacitors, and switched inductors. The front‐end comprises a dual‐gain‐mode narrowband low‐noise amplifier (LNA) and a dual‐linearity‐mode mixer. A four‐mode receiver RF front‐end constructed with the dual‐gain‐mode LNA and the dual‐linearity‐mode mixer operating in frequency band range from 1800 to 2050 MHz was demonstrated with an IBM 90‐nm CMOS process. The front‐end achieves a 1/1.6 dB noise figure, 30/20 dB power gain, and 16/?10 dBm third‐order input intercept point while draws a 5.9/3.6 mA current from a 1.8‐V supply voltage at the low noise mode and high linearity mode, respectively. The proposed technique can be employed to build an intelligent mobile system.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

A 2.4-GHz CMOS transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset     

A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

This paper presents a 1 V RF transceiver for biotelemetry and wireless body sensor network (WBSN) applications, realized as part of an ultra low power system-on-chip (SoC), the Sensiumtrade. The transceiver utilizes FSK/GFSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node in a single-hop star network topology operating in the 862-870 MHz European short-range-device (SRD) and the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands. Controlled by a proprietary media access controller (MAC) which is hardware implemented on chip, the transceiver operates half-duplex, achieving -102 dBm receiver input sensitivity (for 1E-3 raw bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 0.9 to 1.5 V supply. It is fabricated in a 0.13 mum CMOS technology and occupies 7 mm² in a SoC die size of 4 times 4 mm².     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

Radio transceivers for wireless personal area networks using IEEE802.15.4 - [integrated circuits for communications]

This article describes the design considerations for low-power short-range radio transceivers with a focus on the 2.4 GHz PHY layer defined as part of the IEEE 802.15.4 standard. The specification requirements for IEEE 802.15.4-compliant transceivers, and the design challenges and practical implementation of a highly-integrated low-power 2.4 GHz transceiver are subsequently discussed. The transceiver uses a direct-conversion receiver with switched antenna diversity and a transmitter using direct closedloop VCO modulation. It integrates a mask-programmable radio controller capable of autonomously performing timing-critical MAC functions, and a sleep timer. Implemented in 0.18 mum RFCMOS technology with a chip area of less than 6 mm², the transceiver achieves a link margin of 99 dB while drawing 16.8 mA and 18 mA from a 1.8 V supply in receive and transmit mode, respectively.