Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

Active‐matrix organic light‐emitting displays employing two thin‐film‐transistor a‐Si:H pixels on flexible stainless‐steel foil

Abstract— An active‐matrix organic light‐emitting diode (AMOLED) display driven by hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) on flexible, stainless‐steel foil was demonstrated. The 2‐TFT voltage‐programmed pixel circuits were fabricated using a standard a‐Si:H process at maximum temperature of 280°C in a bottom‐gate staggered source‐drain geometry. The 70‐ppi monochrome display consists of (48 × 4) × 48 subpixels of 92 ×369 μm each, with an aperture ratio of 48%. The a‐Si:H TFT pixel circuits drive top‐emitting green electrophosphorescent OLEDs to a peak luminance of 2000 cd/m².     

Bezel free design of organic light emitting diode display via a‐InGaZnO gate driver circuit integration within active array

In this article, we described an innovative design technology of active matrix organic light emitting diode (AMOLED) display, to provide a bezel free design. We designed gate driver circuit of amorphous indium‐gallium‐zinc oxide thin‐film transistors (TFTs) not on the bezel area but within the active array. Although we applied challengeable design, no degradation of electrical/optical properties of panel was observed. Because we effectively prevented capacitive coupling and interference between the emission circuit and integrated gate driver circuit in active array, finally, we successfully demonstrated a bezel free designed AMOLED display of 18.3″ HD (1366 × 768) driven by a‐InGaZnO TFTs.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Active‐matrix organic light‐emitting diode using inverse‐staggered poly‐Si TFTs with a center‐offset gated structure

Abstract— A low‐cost active‐matrix backplane using non‐laser polycrystalline silicon (poly‐Si) having inverse‐staggered TFTs with amorphous‐silicon (a‐Si) n⁺ contacts has been developed. The thin‐film transistors (TFTs) have a center‐offset gated structure to reduce the leakage current without scarifying the ON‐currents. The leakage current of the center‐offset TFTs at Vg = ?10 V is two orders of magnitude lower than those of the non‐offset TFTs. The center‐offset length of the TFTs was 3 μm for both the switching and driving TFTs. A 2.2‐in. QQVGA (1 60 × 1 20) active‐matrix organic light‐emitting‐diode (AMOLED) display was demonstrated using conventional 2T + 1C pixel circuits.     

Characteristics and stability of improved re‐crystallized metal‐induced laterally crystallized polycrystalline‐silicon thin‐film transistors for display applications

Abstract— The performance of high‐temperature re‐crystallized (RC) metal‐induced laterally crystallized (MILC) polycrystalline‐silicon (poly‐Si) thin‐film transistors (TFT) have been improved by (1) patterning the active islands before MILC, (2) removing nickel‐containing residues using acid cleaning, (3) using heavily boron‐doped poly‐Si gates to achieve threshold voltage symmetry, and (4) double‐implanting n‐type source/drain junctions. A 30‐MHz driver circuit based on this improved technology was demonstrated. The reliability of optimized RC‐MILC poly‐Si TFTs has not been adversely affected by residual nickel‐containing contaminants in the TFT channel regions.     

Development of a 10.4‐in. UXGA display using low‐temperature poly‐Si technology

A new 10.4‐in.‐diagonal display with UXGA resolution (1600 H × 1200 V pixels) using low‐temperature polysilicon (poly‐Si) TFTs has been developed for notebook‐PC applications. The source drive technique uses integrated selector switches, which decreases the number of tape carrier packages (TCPs) for a poly‐Si TFT‐LCD and increases the connection pitch of the TCPs to the glass substrate. In this paper, we present a new display configuration and fabrication process.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

PECVD films for low‐temperature poly‐Si TFT‐LCD applications

Low‐temperature polycrystalline‐silicon (poly‐Si) thin‐film‐transistor (TFT) processes, based on PECVD amorphous‐silicon (a‐Si:H) precursor films and excimer‐laser crystallization, have been developed for application in the fabrication of active‐matrix liquid‐crystal‐displays (AMLCDs). The optimum process for depositing the precursor films has been identified. The relationship between excimer‐laser crystallization and poly‐Si film morphology has also been studied. Using these techniques, poly‐Si TFTs with a mobility of 275 cm²/V‐sec and on/off ratios of 1 × 10⁷ have been fabricated.     

Current programming pixel circuit and data‐driver design for active‐matrix organic light‐emitting diodes

Abstract— We propose a new pixel design for active‐matrix organic light‐emitting diodes (AMOLEDs) employing five polycrystalline thin‐film transistors (poly‐Si TFTs) and one capacitor, which decreases the data current considerably in order to reduce the charging time compared with that of conventional current‐mirror structures. Also, the new pixel design compensates the threshold‐voltage degradation of OLEDs caused by continuous operation and the non‐uniformity of poly‐Si TFTs due to excimer‐laser annealing. The proposed pixel circuit was verified by SPICE simulation, based on measured TFT and OLED characteristics. We also propose current‐data‐driver circuitry that reduces the number of shift‐register signals for addressing the current data driver by one‐half.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

Abstract— A complete poly‐Si thin‐film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active‐matrix displays. We present a detailed study of the poly‐Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high‐performance low‐temperature gate dielectric film. Poly‐Si grain sizes and the corresponding TFT performance have been measured for a range of excimer‐laser crystallization fluences near the full‐melt threshold, allowing optimization of the laser‐crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer‐laser pulse is described. Finally, we describe a plasma pre‐oxidation step, which has been added to a low‐temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly‐Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm² /V‐sec, threshold voltages of ?3.5 V, and off currents of approximately 1 pA per micron of gate width.     

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.     

Amorphous‐silicon thin‐film transistor on soda‐lime glass

Abstract— Amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) on soda‐lime glass were fabricated by using a diffusion barrier and a low‐temperature process at 200°C. The silicon nitride barrier was optimized in terms of diffusion blocking effectiveness, film adhesion, and surface finish. TFTs on soda‐lime glass achieved a saturation mobility 0.47 cm²/V‐sec, threshold voltage of 0 V, an off‐current of 7.7×10^?11 A, and a sub‐threshold swing of 1.0 V/dec. From diffusion experiments, a 30,000‐hour lifetime for the TFT device at 80°C was estimated, and the robustness of the silicon nitride barrier against long‐term migration of sodium was demonstrated.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Current and future technology of low‐temperature poly‐Si TFT‐LCDs

Abstract— The state of the art of large‐area low‐temperature TFT‐LCDs will be reported in this paper. High‐performance poly‐Si TFTs are expected to realize various applications such as system display where various signal‐processing functions are added to the display. In the past few years, low‐temperature poly‐Si thin‐film‐transistor (LTPS TFT) technology has made great progress, especially in the areas of excimer laser annealing (ELA) of high‐quality poly‐Si film, ion doping for large‐area doping, and high‐quality gate SiO₂ film formation by using the low‐temperature PE‐CVD method. Also, technology trends and possible applications, such as a system displays, will be discussed.     

Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 10¹¹ cm^?2/eV and Nss = 7.0×10¹⁶ cm^?3/eV for the unannealed TFT, which increased to 5.2×10¹¹ cm^?2/eV and 9.8×10¹⁶ cm^?3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×10¹¹ cm^?2/eV and Nss = 3.2×10¹⁶ cm^?3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.