n-GaAs和p-GaN晶片的直接键合

采用直接键合的方法成功实现了n-GaAs和p-GaN晶片的高质量键合.扫描电子显微镜观测结果表明,键合界面没有空洞.键合前后光致发光谱测试表明,键合工艺对材料质量影响不大.室温下界面的电流-电压特性表明,键合得到的n-GaAs/p-GaN异质结为肖特基二极管并且理想因子为1.08.n-GaAs和p-GaN材料直接键合的成功对于集成GaAs和GaN材料制备光电集成器件有重要意义.     

基于亲水表面处理的GaAs/GaN晶片直接键合

对晶片进行亲水表面处理,在氮气保护下500℃热处理10min,成功实现GaAs与GaN晶片的直接键合,键合质量较好.扫描电子显微镜观测结果表明,键合界面没有空洞.光致发光谱观测结果表明,键合工艺对晶体内部结构的影响很小.可见光透射谱测试结果表明,键合界面具有良好的透光特性.GaAs与GaN晶片直接键合的成功,为实现GaAs和GaN材料的集成提供了实验依据.     

基于亲水表面处理的GaAs/GaN晶片直接键合

对晶片进行亲水表面处理,在氮气保护下500℃热处理10min,成功实现GaAs与GaN晶片的直接键合,键合质量较好.扫描电子显微镜观测结果表明,键合界面没有空洞.光致发光谱观测结果表明,键合工艺对晶体内部结构的影响很小.可见光透射谱测试结果表明,键合界面具有良好的透光特性.GaAs与GaN晶片直接键合的成功,为实现GaAs和GaN材料的集成提供了实验依据.     

基于硫化物表面处理的InP/GaAs低温晶片键合

提出一种新的基于硫化物表面处理的InP/GaAs低温晶片键合技术.在360℃的退火温度下,获得了1.2MPa的键合强度.基于这种低温键合技术,可将外延生长在InP衬底上的In0.53Ga0.47As/InP多量子阱(MQW)键合并转移到GaAs衬底上.X射线衍射表明量子阱的结构未受键合过程的影响.光致发光谱分析表明键合后量子阱的晶体质量略有改善.电流电压特性的测试表明n-InP/n-InP的键合界面具有良好的导电特性;在n-InP/n-GaAs 的键合界面存在着电荷势垒,这主要是由于键合界面存在GaAs氧化物薄层所致.     

乙二醇辅助多层硅/硅直接键合

利用乙二醇的分子结构和氢键在10万级的超净环境下成功地进行了多层乙二醇环境下的硅/硅直接键合,并在氮气保护下1100℃热处理后进行了拉力强度测试,平均键合强度达到了10MPa.SEM观测表明,在键合界面没有发现孔洞和空隙.该方法同样适用于Ⅲ-Ⅴ族化合物的直接键合.这为发展多层结构、多功能集成的MEMS结构器件奠定了良好的工艺基础.     

键合技术的研究进展及应用

晶片直接键合技术是材料集成的一项新工艺,是近年来集成光电子领域的研究热点之一.利用键合技术可以集成晶格或晶向失配的材料,制造传统外延生长技术不能制造的结构和器件.概括介绍了近年来Ⅲ-V族化合物半导体材料键合技术的最新研究进展及其在光电子器件和集成领域的应用.     

一般性问题

TN052005060001键合技术的研究进展及应用/王慧,沈光地,高国,梁庭(北京工业大学光电子实验室)//半导体技术.―2005,30(7).―6～10.晶片直接键合技术是材料集成的一项新工艺,是近年来集成光电子领域的研究热点之一。利用键合技术可以集成晶格或晶向失配的材料,制造传统外延生长技术不能制造的结构和器件。概括介绍了近年来III-V族化合物半导体材料键合技术的最新研究进展及其在光电子器件和集成领域的应用。图5表0参19一般性问题     

基于硫化物表面处理的InP/GaAs低温晶片键合

提出一种新的基于硫化物表面处理的InP/GaAs低温晶片键合技术．在360℃的退火温度下，获得了1.2MPa的键合强度．基于这种低温键合技术，可将外延生长在InP衬底上的In0.53Ga0.47As/InP多量子阱（MQW）键合并转移到GaAs衬底上．X射线衍射表明量子阱的结构未受键合过程的影响．光致发光谱分析表明键合后量子阱的晶体质量略有改善．电流电压特性的测试表明n-InP/n-InP的键合界面具有良好的导电特性；在n-InP/n-GaAs的键合界面存在着电荷势垒，这主要是由于键合界面存在GaAs氧化物薄层所致．     

化合物半导体晶片和器件键合技术进展

半导体晶片直接键合技术已成为半导体工艺的一门重要技术 ,它对实现不同材料器件的准单片集成、光电子器件的性能改善和新型半导体器件的发展起了极大的推动作用。文中详细叙述了近十年来 - 族化合物半导体键合技术的主要实验方法 ,并对各种键合方法的优缺点进行了比较 ,结合自己的工作对化合物半导体的键合机理和界面特性做了总结 ,针对目前的研究工作和应用做了展望     

乙二醇辅助多层硅/硅直接键合

利用乙二醇本身的分子结构和氢键在10万级的超净环境下成功进行了多层乙二醇环境下的硅/硅直接键合,在氮气保护下1100℃热处理后进行了拉力强度测试,平均键合强度达到了10Mpa,SEM观测表明,在键合界面没有发现孔洞和空隙。这为发展多层结构、多功能集成的MEMS结构器件奠定了良好的工艺基础。     

直接键合四结GaAs太阳电池研究

晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。     

基于硼酸溶液处理的GaAs/InP低温晶片键合技术

提出了一种基于硼酸溶液的GaAs/InP低温晶片键合技术,实现了GaAs/InP基材料间简单、无毒性的高质量、低温(290℃)晶片键合。GaAs/InP键合晶片解理截面的扫描电子显微镜(SEM)图显示,键合界面整齐,没有裂缝和气泡。通过键合过程,InP上的In0.53Ga0.47As/InP多量子阱结构转移到了GaAs基底上。X射线衍射及荧光谱显示,键合后的多量子阱晶体质量未变。二次离子质谱(SIMS)和Raman光谱图显示,GaAs/InP键合晶片的中间层厚度约为17 nm,界面处B元素有较高的浓度,键合晶片的中间层很薄,因此可以得到较好的电学、光学特性。     

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed     

Direct wafer bonding of III-V compound semiconductors forfree-material and free-orientation integration

This paper describes the use of direct wafer bonding technique to implement the novel concept of “free-material and free-orientation integration” which we propose. The technique is applied for various wafer combinations of an InGaAsP material system, and the properties of the bonded structures are studied in terms of the crystalline and electrical characterization through transmission electron microscope, X-ray diffraction, and so on. This technique's advantage for use in the fabrication of lattice-mismatched structures is confirmed by the crystalline characterization, together with its second advantage of enabling bonded structures with an orientation mismatch, is investigated. The high crystalline quality of the bonded structures with both lattice and orientation mismatches is proved, and the electrical property of the bonded interface is examined for some of them. We show a practicability in a laser fabricated on a lattice- and orientation-mismatched structure by direct bonding. The results demonstrate the remarkable feasibility of using the direct wafer bonding technique to obtain integrated structures of material- and orientation-mismatched wafers with satisfactory quality     

基于湿法表面活化处理的InP/SOI晶片键合技术

为了实现集成硅基光源,研究了基于湿法表面处理的InP/SOI直接键合技术。采用稀释的HF溶液对InP晶片进行表面活化处理,同时采用Piranha溶液对SOI晶片进行表面活化处理,实现了二者的低温直接键合。分别采用刀片嵌入法和划痕测试仪对样品的键合强度进行了定性及定量分析。同时,采用超声波扫描显微镜及扫描电子显微镜对键合界面的缺陷信息及键合截面的微观特性进行了评估。分析结果表明:提出的键合工艺可以获得较好的键合效果。     

表面翘曲度对晶圆直接键合的影响

根据薄板弯曲理论,推导出晶圆表面翘曲度及夹具形状影响晶圆直接键合的理论公式,很好地解释了晶圆材料性质及尺寸大小对直接键合的影响.利用理论公式比较了晶圆在外压力和无外压力作用下翘曲度对晶圆直接键合的不同影响,结果表明晶圆键合后的形状由晶圆的初始形状及键合所用的夹具决定.最后应用有限元进行了仿真分析,仿真结果表明,晶圆存在一定翘曲度时施加合适的外压力将有助于晶圆的直接键合.     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.     

基于UV光照的圆片直接键合技术

研究了UV辅助活化与湿化学清洗活化相结合的圆片直接键合技术,并利用红外测试系统、单轴拉伸测试仪和场发射扫描电子显微镜,结合恒温恒湿实验、高低温循环实验对键合质量进行了测试.结果表明,采用该技术可以实现较好的圆片直接键合,提高键合强度,控制合适的UV光照时间可以获得更高的强度,对键合硅片进行恒温恒湿和高低温交变循环处理后,硅片仍能保持较高的键合强度.因此,该工艺对于改进圆片直接键合技术是行之有效的,具有很大的应用潜力.     

光路可调的红外透射方法检测键合质量

基于红外透射原理,采用调节光路的冷光源方法搭建了晶片键合界面的质量检测系统。利用该系统可以很好的实现GaAs,InP材料的键合界面检测和刀片分离时的在线监测,同时本文以GaAs基分布布拉格反射镜(DBR)和InP基有源区键合为例,结合红外透视图像和薄膜转移照片分析,对键合表面处理方法进行了优化选择。试验表明该检测系统数据可靠,使用方便,为晶片键合条件及参数优化提供了实用平台。     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.