共查询到18条相似文献,搜索用时 125 毫秒
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介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。 相似文献
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本文描述了一种新型的多量子阱空间光调制器驱动电路的设计和测试。为了解决时钟同步问题并减少功耗,我们有别于前人,将所有电路模块集成在一块芯片上。因为传统的单斜坡数模转换器无法消除电容的失配,所以我们转而采用64个列共享8位电阻串数模转换器来提供输出电压,实现0.5V至3.8V的可编程电压调控。这些数模转换器被紧密放置于6464 驱动阵列的上方力求减小失配。每个转换器消耗80uA电流,在280ns内完成一次转换。为了更快的传输速率,系统采用2级缓存,工作时钟50MHz,真刷新率达到50K帧每秒,整片功耗302mW。芯片采用0.35um CMOS工艺,面积5.5 mm7 mm。 相似文献
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《固体电子学研究与进展》2013,(5)
电流舵型数模转换器(DAC)广泛应用于通信系统。采用电流分叉结构的电流舵型DAC可以极大地减小电流源阵列的面积。提出一种可以应用于采用电流分叉结构的电流舵型DAC的数字校准技术。提出的后台校准技术可以同时消除高位电流源阵列和低位电流源阵列的失配误差。基于0.18μm CMOS工艺,设计并流片了一款14bit 200MS/s电流舵型DAC,经过数字校准后,无杂散动态范围(SFDR)能够提高至少24dB。在时钟频率为200MS/s,输出信号为2MHz时,SFDR能够达到80dB以上。芯片面积为1.26mm2,功耗为125mW。 相似文献
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程龙林宇婧叶凡李宁任俊彦 《固体电子学研究与进展》2013,(5):472-478
电流舵型数模转换器(DAC)广泛应用于通信系统。采用电流分叉结构的电流舵型DAC可以极大地减小电流源阵列的面积。提出一种可以应用于采用电流分叉结构的电流舵型DAC的数字校准技术。提出的后台校准技术可以同时消除高位电流源阵列和低位电流源阵列的失配误差。基于0.18μm CMOS工艺,设计并流片了一款14bit 200MS/s电流舵型DAC,经过数字校准后,无杂散动态范围(SFDR)能够提高至少24dB。在时钟频率为200MS/s,输出信号为2MHz时,SFDR能够达到80dB以上。芯片面积为1.26mm2,功耗为125mW。 相似文献
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Ivan Harald Holger Jørgensen Svein Anders Tunheim 《Analog Integrated Circuits and Signal Processing》1997,12(1):15-28
This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8µm BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of approximately 650mW. The area of the chip-core is 2.2mm × 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f
g0.1 f
s(f
s = 100MSamples/s) the measured SFDR is 50dB, and at f
g0.3 f
s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase. 相似文献
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Greenley B. Veith R. Dong-Young Chang Un-Ku Moon 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2005,52(5):246-250
A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings. 相似文献
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The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal crosspoint and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz. 相似文献
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《Solid-State Circuits, IEEE Journal of》1985,20(6):1133-1137
An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/'s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher. 相似文献
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针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源... 相似文献
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Dongwon Seo 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(6):1455-1463
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Shu-Chung Yi 《International Journal of Electronics》2013,100(9):1291-1298
In this article, a digital to analogue converter (DAC) based on multi-weighted current sources is proposed. This research requires only three kinds of current sources for a 6-bit DAC. The proposed DAC is implemented by 0.18?µm CMOS technology. The post-layout simulations of integral nonlinearity and differential nonlinearity are 0.076 and 0.099?LSB, respectively. The core area of the chip is 640?µm2. The DAC consumes 3.5?mW at the sample rate of 1.6?GHz with a supply voltage of 1.8?V. The specifications of the proposed DAC make it suitable for a portable device. 相似文献
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Welz J. Galton I. 《IEEE transactions on information theory / Professional Technical Group on Information Theory》2004,50(4):593-607
Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits. 相似文献